Agenda

The SNUG World agenda features over 200 sessions and is arranged by day and track. Select the day below to see the full detailed agenda. Use the filters to view the daily technical sessions by track to plan your time at SNUG World. Once you’ve selected the filters, click on the day link for results.

  • All times are listed in Pacific Time (PT), select sessions will begin at 7 AM PT to accommodate the global community.
  • Daily keynotes are scheduled at 9 AM PT.
  • *Denotes user content reviewed by the SNUG World Technical Committee
  • The following tracks are only scheduled on one day of the program: Day 1: Secure, Safe & Reliable and Day 2: IP.
  • For your convenience, Verification sessions are broken up into several tracks across the three days: Emulation, Formal Verification, New Verification Technologies, Prototyping, Static Verification, VCS/Verdi/VIP and Virtual Prototyping.
  • Click here to see the At-a-glance Agenda

Session Days

Tracks

7:00 AM - 7:50 AM

Building a Trustworthy Autonomous Vehicle (AV) Architecture

Track: Automotive

Hardware ASIC / System Safety are key enablers for the overall robustness and dependability of autonomous vehicle architectures. Indeveloping functional safety that addresses hardware random failures and systematic failures, it is also crucial to consider cybersecurity and safety of intended functionality (SOTIF). In this keynote, well cover NVIDIAs vision for functional safety, as well as our work with various international governing standards and regulations. The talk will also include an overview of the standard IEEE P2851, which aims to provide an exchangeable and interoperable format for safety analysis and safety verification activities at IP, SoC and system levels.The standard addresses interoperability challenges of dependable systems covering functional safety, SOTIF, cybersecurity and other characteristics such as reliability, maintainability and real time.

Presenter
Riccardo Mariani

NVIDIA

Presenter
Jyotika Athavale

Senior Functional Safety Architect, NVIDIA

8:00 AM - 8:25 AM

CNN Acceleration: A Short Road Trip

Track: Automotive

Convolutional Neural Networks (CNN) are widely adopted for various computer vision tasks. They are also gaining traction in the auto-motive industry. As such, front-view cameras may rely on CNNs for semantic segmentation and object detection. They typically require very performant and very efficient CNN accelerators. The presentation will give a brief overview of CNNs in general. It will explain the use of CNNs for semantic segmentation and object detection and describe some CNNs designed for these tasks. It will discuss the challenges of embedding a CNN accelerator in a SoC and of providing a SW tool chain that enables the full performance and efficiency of the CNN accelerator. It will describe the performance results generated by Bosch using Synopsys' DesignWare ARC EV processor and CNN engine with 3520 MACs.

Presenter(s)
Filip Moerman

System Architect, Bosch

8:25 AM - 8:50 AM

Accelerate the Development of Dependable Automotive SoCs with Synopsys' Comprehensive Safety-Aware Solution

Track: Automotive

At higher levels of autonomy, the autonomous driving (AD) compute solution will become more centralized to rapidly fuse multimodal sensor data and safely choose and initiate self-driving actions. Complex automotive SoCs with purpose-built processors to increase computational efficiency require automotive-grade IP and ISO 26262-certified safety-aware design and hardware and software verification solutions to meet strict design targets to achieve target ASIL. Before silicon is available, early development and testing of safe and secure software relies on virtualized hardware. Synopsys partners with automotive market leaders and new entrants to accelerate development of safety-critical SoC. In this session, we present Synopsys safety-aware expertise, IP and tool solution to help reduce cost, alleviate risk and accelerate go-to-market.

Presenter(s)
Stewart Williams

Senior Automotive Vertical Marketing Manager, Synopsys

9:00 AM - 9:50 AM

Welcome to a Bold New Era of Moore’s Law

Track: KEYNOTE

Even for an industry hardened against systemic and scale complexity, building a world with 1000X more compute by the end of the decade will require revolutionary approaches to architecture, groundbreaking autonomous design systems, and disruptive engineering from cloud to edge. Founder and co-CEO Aart de Geus is set to lift the veil on a highly anticipated portfolio of design instruments that will ignite an era of exponential opportunity for humankind, and shine as a beacon of the Synopsys “Yes, if…” spirit of limitless possibility.

Presenter(s)
Dr. Aart de Geus

Chairman and co-Chief Executive Officer, Synopsys

10:00 AM - 10:50 AM

Executive Panel: How is AI Changing the Way We Approach Chip Design?

Track: Artificial Intelligence

The semiconductor industry is entering a Cambrian era of innovation. A plethora of domain-specific architectures are heralded as the answer to overcoming the slowing of Moore’s Law – but can design teams scale? Can AI enable a path to 1,000X compute performance and energy efficiency? Our executive discussion panel of industry leaders will weigh-in on the promise of AI for chip design, drawing from real-world experiences.

Moderator
Stelios Diamantidis

Synopsys

Panelist
Artour Levin

Intel

Panelist
Paul Penzes

Qualcomm

Panelist
Sangyun Kim

Samsung Electronics

Panelist
Thomas Andersen

Synopsys

10:00 AM - 10:25 AM

Influence of Dynamic Driving Model on SoC Development and IP Selection

Track: Automotive

Engineering an autonomous driving (AD) system requires a thorough understanding of the dynamic interaction between driver, vehicle, and environment. A dynamic model at the driving level enables design of an E/E network architecture with E/E systems as acting nodes which meets the customer expectation. In this presentation we discuss why the success of the SoC design architecture is highly dependent on the dynamic model of the ADAS/AD feature at the driving level. Key requirements include assigning the appropriate sense, control, and actuation functions to the SoC, laying out the SoC function with sufficient performance (SOTIF), avoiding and mitigating random and systematic faults (functional safety), and preventing malevolent intrusion to the SoC and from there into the whole E/E network (security).

Presenter(s)
Bernhard Bauer

Product Safety Expert, Synopsys

10:00 AM - 10:25 AM

Accelerating Semiconductor Design and Verification using Cloud Optimized EDA Solutions from Synopsys

Track: Cloud

Synopsys technologists have been driving key innovations in our products across the portfolio to deliver differentiated cloud optimized solutions to our customers. In this session we will share examples of this journey and how these innovations are helping our customers to accelerate their design implementation and verification by maximizing the benefits from cloud environments.

Presenter(s)
Sandeep Mehndiratta
10:00 AM - 10:25 AM

AMS Simulation Update

Track: Custom - AMS

Learn how the latest advancements in circuit simulation can help you reduce the turnaround time of your analog/mixed-signal and memory designs while improving the quality of results.

Presenter(s)
Hany Elhak

Sr. Director, Product Management and Marketing, CPG, Synopsys

10:00 AM - 10:50 AM

Successful 2.5D and 3D Multi-die Silicon System Design using Synopsys' 3DIC Compiler and Ansys' Multiphysics Analysis

Track: Digital Design

Due to Moore's law diminishing and the increased cost of silicon, repartitioning large System-On-Chip (SoC) into smaller chiplets and stacking technologies has become attractive for IC design teams. High-Bandwidth Memory, consisting of stacked DRAMs connected directly through a short interposer link to a GPU/CPU or TPU, called 2.5D, delivers drastic performance and cost improvements. The evolution is 3D, silicon systems built on many layers of GPU, CPU, Logic, and Memories. In this session, Synopsys and Ansys will present an end-to-end design and analysis solution for successful 2.5D and 3D integrated circuit designs.

Presenter(s)
Kenneth Larsen

Synopsys

10:00 AM - 10:25 AM

*Compile Time Improvements using Zebu zECO Flow for Debug Methodology

Track: Emulation

This presentation discusses the issue of large turnaround time for emulation model build while entertaining the change requests for new signal forces and new debug probes during an active time-critical debug cycle. Emulation methodology in-general provides fast time to market solutions and any delay is harmful for achieving critical tape-out goals. In a typical emulation case, the model builder would have to put the change requests through a total rebuild, even if the change is limited to merely 1 signal. This costs a lot of time. Hence, our presentation describes a method to churn out emulation models with improved compile time using a Zebu zECO flow. This presentation also provides empirical data to support claims made by Synopsys for Zebu zECO flow for incremental compilation, focussing only on debug ECOs.

Presenter(s)
Chirantan Joshipura

NXP

10:00 AM - 10:25 AM

Energy Efficient Chip Design

Track: Low Power Design

Low power, energy efficiency, and how to manage it – it’s one of the most urgent challenges chip designers face today and the decisions we make can have a real impact on everyone, across the globe. Join our keynote presentation by Intel’s Satya Prabhakar to learn more about the role electronics plays in overall energy consumption and how low power design techniques are driving energy efficiency in some of the fastest-growing segments in electronics industry.

Presenter(s)
Prabhakar S (Satya) Ayyagari

Intel

10:00 AM - 10:50 AM

VC PSS Tutorial

Track: New Verification Technologies

PSS is used to capture functional intent, which can then be used regardless of the verification stage. The functional intent is represented as a stimulus model written in the PSS language. This tutorial will show how Synposys solution enables porting stimulus to many different environments from single source; Generation of many intelligent test cases from a succinct model and creation of coverage-driven, system-level test cases targeting bugs, which are difficult to detect, at the System Level.

Presenter(s)
Alan Curtis

Intel

Presenter(s)
Robert Martin

Intel

Presenter(s)
Bernie DeLay

Synopsys

Presenter(s)
Gopinath Lakshmi Narasimhan

Synopsys

10:00 AM - 10:25 AM

Driving Physical Signoff Convergence at Advanced Technology Nodes

Track: Physical Verification

Increasing design and manufacturing complexities at advanced nodes (7nm, 5nm and below) pose significant challenge for physical verification engineers to achieve on-time design closure. IC Validator continues to innovate in scalable performance, high productivity and robust debugging. In this presentation, TSMC talks about partnership with Synopsys IC Validator on technology collaboration and tool enablement for TSMCs advanced process nodes. Synopsys provides an overview of latest IC Validator innovations for physical verification productivity and how to deploy these technologies to achieve faster physical verification closure.

Presenter(s)
Captain Liu

TSMC

Presenter(s)
Anil Karanam

Synopsys

10:00 AM - 10:50 AM

KEYNOTE - Zero Trust Microelectronics: A Model for Hardware Security Evolution

Track: Secure, Safe & Reliable

Application of Zero Trust principles across the microelectronics lifecycle has the potential to raise confidence in the components available for implementation in safety-critical systems that have an ever-increasing role in society. However, since Dr. Lisa Porter (DUSD(R&E)) advocated for a new Zero Trust paradigm for securing microelectronics at DARPA ERI in 2019, the hardware community has raised concerns regarding the meaning and application of Zero Trust principles for hardware. This presentation returns to the first principles and foundational tenets of Zero Trust established by the cybersecurity community and provides an initial mapping for their application to stages of the hardware lifecycle with the objective of outlining how application of security controls at the appropriate points can uplift the confidence in implemented microelectronics.

Dr. Brian Dupaix currently serves as the Acting Data Driven Quantifiable Assurance Project Area Lead for the Office of the Secretary of Defense (OSD) Trusted & Assured Microelectronics / MINSEC program, managing a research and development budget of over $250M per year. Concurrently, he serves as the Air Force Design Assurance Lead at the AFRL Sensors Directorate in Dayton, Ohio, and is an adjunct professor at The Ohio State University. Dr. Dupaix holds a BS degree Brigham Young University and MS and PhD degrees from The Ohio State University. Prior to joining AFRL, he was a Research Scientist at Ohio States ElectroScience Laboratory, working on high-speed DACs and ADCs, III-V power-amplifiers, mixed-signal reliability, and trusted electronic components. He also worked in industry, spending 5 years at Honeywell Air Transport Systems, designing digital ASICs for commercial flight and navigation systems and 4 years at Intrinsix creating IP blocks for extensible processors and System-on-Chip ASICs for consumer electronics. He has published over 40 papers and holds five patents with several pending.

Presenter(s)
Dr. Brian Dupaix

Principal Engineer at the AFRL Sensors Directorate, AFRL

10:00 AM - 10:25 AM

*Min-Max Contention Aware Clock Planning in Mega Hierarchical Designs

Track: Signoff I

As the industry moves to advanced technology nodes with smaller transistors and increasingly bigger design size, the On-Chip Variation (OCV) impact becomes more significant. OCV shrinks the timing window, posing huge challenge to timing convergence. This is especially true when the timing paths cannot be converged when they hit min-max contention. To prevent this, careful clock planning is crucial to minimize the point of divergence and reduce the OCV. Often times, clock planning at the early stage of the design is not accurate without mature design data. Thus, this presentation shares an innovation of which the designers can perform clock planning with minimum design data, while still achieving satisfactory OCV and min-max contention estimation. This data can be used to guide the clock trunk and clock trees implementation with minimum OCV. Furthermore, it can also be used as implementation specification in hierarchical based designs, enabling correct by construction sub blocks.

Presenter(s)
Wan Chong Khor

Technical Lead, Intel

10:00 AM - 10:25 AM

Cost-Effective Characterization on Arm based AWS Graviton2 Processors Using SiliconSmart®

Track: Signoff II

Characterization is a compute intensive exercise and the demands are growing by the day to capture more views in more accurate forms. Moments LVF, high-sigma accurate requirements, EM are a few examples of more views emerging in more accurate forms, pushing the demand for compute through the roof, when factoring shrinking time-to-market requirements. While everyone’s working hard to innovate to address these challenges, we at Arm, in collaboration with Synopsys, present our contribution to this game by marrying two concepts – Cloud Computing and Arm-Core Execution. Cloud computing offers amazing scalability with the right mix of software and configuration, thereby helping us meet the compute demands emanating from our time-to-market requirements. However, there is a cost associated and this must be profitable over the incumbent on-premises approach, to turn heads. This is where Arm based AWS Graviton2 processors comes into picture, they are not only fast but also cost effective hence execution on Arm-powered cores, instead of the conventional x86-powered cores, is the magic wand that helps us achieve our objectives.

Presenter(s)
Ajay Chopra

Director, Arm

10:00 AM - 10:25 AM

TestMAX Manager for RTL-Based Test Flow

Track: Silicon Test and Analytics

Under pressure to meet design schedules, design-for-test (DFT) engineers and teams must quickly architect, implement and validate increasing complex DFT logic. The complexity continues to rise as the challenge to meet manufacturing test quality and cost goals for many newer-generation designs are met by using sophisticated test techniques. This session will provide an overview and relevant details of Synopsys TestMAX Manager and new flow guidance to enable easy implementation of major RTL DFT components such as compression logic, logic BIST, memory BIST, and access networks. In addition, connections to DFT functionality validation will be covered as well as connections to synthesis-based test for lower-level, essential DFT (example: scan chains), accelerating the entire DFT effort.

Presenter(s)
Tammy Fernandes

Sr. Staff, Synopsys

10:00 AM - 10:25 AM

*Hierarchical CDC Verification on Billion Gates

Track: Static Verification

The verification of Clock Domain Crossing (CDC) issues on billion gate SoCs had become unmanageable due to issues previously analyzed at block-level re-surface, and multiple days of run-time and capacity issues. We will present the hierarchical CDC verification flow we used to demonstrate the need to focus on inter-block CDC issues at SoC level, saving run time and distributing analysis time and effort.

Presenter(s)
Harish Aepala

Facebook

10:00 AM - 10:25 AM

VCS Performance Updates & What's New?

Track: VCS/Verdi/VIP

Learn more about boosting simulation performance with FGP, distributed compile and other performance related enhancements.

Presenter(s)
Rohit Narkar

Synopsys

10:25 AM - 10:50 AM

Samsung Foundry's Automotive Reference Flow

Track: Automotive

Automobiles must operate in a safe, reliable and secure manner, especially in next-generation autonomous driving and advanced driver-assistance systems (ADAS) applications. E/E systemsin such vehicles, such as SoC designs, shouldcomply withthe ISO 26262 standard to achieve functional safety which is specified by automotive safety integrity level (ASIL). Samsung Foundry will present how their automotive reference flow is using Synopsyss comprehensive automotive solutions that help their customers meet their target ASILs.

Presenter(s)
Eunju Hwang

Samsung Electronics

10:25 AM - 10:50 AM

Hybrid EDA Workloads in Public Cloud

Track: Cloud

Enabling EDA workloads in public cloud creates flexibility in engineering execution during compute demand peaks by providing the ability for key workloads to run in hybrid cloud mode. Static Timing Analysis is one of the most compute/memory intensive workflow for peak shaving, Qualcomm worked with Synopsys R&D to enable this capability in AWS . Some challenges faced were how STA is complex to execute and reside at tail end of design cycle, leaving little tolerance for delay. In summary, EDA workloads in the cloud have demonstrated equal or better performance in AWS vs. on premises.

Presenter(s)
Anupama Asthana

Director, IT, Qualcomm

10:25 AM - 10:50 AM

Panel: The Future of Simulation Hardware

Track: Custom - AMS

Learn the latest industry trend on hardware changes that help with simulation performance.

Moderator
Aveek Sarkar

Synopsys

Panelist
Jay Parks

Micron

Panelist
Preeth Chengappa

Microsoft

Panelist
Ting Ku

NVIDIA

Panelist
Mark Han

Synopsys

10:25 AM - 10:50 AM

*Emulation Model Optimizations: Improving Build and Runtime Performance for Benchmarking

Track: Emulation

SOC teams have a key responsibility of running consumer benchmarks and providing performance signoffs during early RTL development phases. These benchmarks take significant time to run in simulation, and an emulation platform like Zebu can offer substantial speedup. Due to specific performance signoff requirements, the benchmark may need to run thousands of iterations, taking several days to complete! Additionally, based on the feedback from benchmark runs, it is desirable to explore varied design configurations, so frequent model builds can be necessary. Given that key architecture decisions are made based on analysis of benchmark runs, improved turnaround for runtime and build is critical to minimize impact on SOC milestones. This presentation discusses in detail the various experiments that were pursued to improve both the model build and runtime turnaround. Results will show how these optimizations significantly improved runtime and build time to enable SOC team to meet their signoffs.

Presenter(s)
DLynn Brandenberger

NXP

Presenter(s)
Avinash Munshi

NXP

10:25 AM - 10:50 AM

Synopsys Low Power Solution, from Architecture to Signoff

Track: Low Power Design

Low power, energy-efficient SoC design requires accurate analysis of dynamic power driven by real-world applications, and the ability to satisfy key power constraints throughout the design flow. This session highlights the Synopsys Low Power Solution and the key technologies enabling low power design starting from architecture, through RTL design and implementation, and leading to power signoff.

Presenter(s)
Godwin Maben

Synopsys

10:25 AM - 10:50 AM

Shift-Left LVS Closure: IC Validator Explorer LVS

Track: Physical Verification

IC Validator Explorer LVS provides a fast and automated way to find root causes of the early full-chip LVS issues. By swiftly detecting design issues, Explorer LVS delivers results up to 30x faster than a traditional LVS flow, enabling more frequent and shorter iterations of running/debugging/fixing design issues and eventually faster LVS sign-off closure.

Presenter(s)
Jinsik Yun

Staff Corporate Application Engineer for IC Validator, Synopsys

10:25 AM - 10:50 AM

Small Range Hold Fixing with LoadCap Cell in PrimeTime

Track: Signoff I

Setup violations implies targeted frequency cannot be achieved but still it can be managed by reducing clock frequency, whereas hold violation are mandatory to fix beforehand because hold failure at silicon is very risky. There are various methods for fixing hold violations, from inserting buffer, delay cells to cell downsizing, and usage of multiple threshold voltage cells. Often during hold fixing, problems of routing congestion or increased leakage occur due to insertion of additional buffer and delay cells, and delay introduced in timing critical paths can lead to setup violations. This presentation describes usage of LoadCap cells to fix minor hold violations less than 10 ps in a congested design with negligible impact on design frequency, area and power. It also describes various details about design, characterization and its usage in Primetime, along with result verified over a digital block at Timing Signoff level.

Presenter(s)
Anuradha Ray

Senior Staff Engineer, STMicroelectronics

Presenter(s)
Tarun Chawla

Staff CAD Engineer, STMicroelectronics

10:25 AM - 10:50 AM

Massive Scalability to 120k Cores for Library Characterization

Track: Signoff II

Library Characterization has typically been a long pole in a design cycle. With ever more demand for accuracy at lower technology nodes, liberty formats has evolved, and the more intricate amount of data help static timing/power analysis and place and route tools to reduce signoff pessimisms. This comes with a cost of simulating more data. To deliver this in a timely manner, highly distributed, massive computing resources are required. Massive scaling of distributed computing resources requires the balance between the handling of the hardware, the handshake between the resource management system and the application being executed. Using parallel distribution technique, systematic partition of the data systems and license check out scheme, we were able to scale our library characterization from a typical compute farm of 30k CPUs to 120k CPUs, allowing us to quadruple the throughput where necessary when additional characterizations are needed on an on demanded basis.

Presenter(s)
Bhargavi Pothula

Intel

10:25 AM - 10:50 AM

TestMAX Manager Flow for Scan Static Timing Analysis (STA) Optimization

Track: Silicon Test and Analytics

TestMAX Manager flow was used in an Intel SoC project for design-for-test (DFT) implementation, providing a highly automated process to insert scan IP at the RTL level as well as generating design constraints that were passed to synthesis and physical design integration. This Intel SoC design was one of the pilot projects that adopt a complete TestMAX Manager flow from RTL to GDS. This project demonstrates a large scale design with a complex design structure. Though TestMAX Manager flow provides an integrated scan IP insertion, scan synthesis and timing constraints, there are significant design specific modifications needed to overcome the challenges caused by complicated clock tree design. This presentation provides an in-depth analysis of the on-chip clock (OCC) controller and clock structure. It also gives a practical static timing analysis (STA) scan constraint guideline that can be referenced in other similar designs.

Presenter
Peng A Cheng

Intel

10:25 AM - 10:50 AM

*CDC Multi Mode Analysis

Track: Static Verification

When two or more asynchronous functional clocks are muxed then regular CDC validation is cumbersome to analyze the results due to many false errors. With ever increasing CHIP complexity, having a number of async clock sources muxed, CDC analysis becomes very complex due to multiple clock modes. For every functional clock mode (source selected from clk mux), we need to run independent CDC in current CDC methodology. Individual CDC runs across modes have duplicated reporting & SVA assertions. With the new Multi-Mode feature in Spyglass, all functional clock modes can be run in a Single CDC JOB and simplified consolidated report is generated and consolidated SVA files are generated. This helped us to save the CDC analysis time and also SVA validation time by half.This presentation outlines the methodology for the CDC Multi-Mode feature and benefits.

Presenter(s)
Ramananda Reddy Bhimireddy

Qualcomm

10:25 AM - 10:50 AM

Automated VCS Dynamic Performance Optimization (DPO) using AI/ML Techniques

Track: VCS/Verdi/VIP

In this session we present DPO, an AI/ML based VCS simulator performance optimizer that targets significant simulation TAT reduction. It is a highly automated system that analyzes the simulation environment, identifies and optimizes performance bottlenecks. We present the practical process, methodology and results deployment on DPO on a production environment.

Presenter(s)
Vamsi Krishna Doppalapudi

Synopsys

11:00 AM - 11:25 AM

*Mozart - An HBM2-Based AI Accelerator

Track: Artificial Intelligence

SimpleMachines has introduced to market its PCIe-based AI accelerator, Mozart. This 16nm chip is able to accommodate large, complex, and fast-changing AI models thanks to two HBM2 memory stacks that sit next to the main compute die. Mozart uses hardened HBM2 and PCIe PHY IPs from Synopsys for its IO interfaces, and has been implemented using a predominantly Synopsys-based tool flow. The chip was designed in one year in close partnership with Synopsys and was successfully brought up in the lab within a week. This presentation describes the IP integration and tool flow challenges encountered during Mozart’s design process, and their successful mitigation by Synopsys and SimpleMachines. In particular, we describe how interposer-based designs can be created where GDS, hard-IP, interposer, and test-and-manufacture are handled by different vendors, and the methodology that can result in a successful and fast silicon bring-up.

Presenter
Preyas Shah

SimpleMachines

11:00 AM - 11:50 AM

Replay: Building a Trustworthy Autonomous Vehicle (AV) Architecture

Track: Automotive

Hardware ASIC / System Safety are key enablers for the overall robustness and dependability of autonomous vehicle architectures. Indeveloping functional safety that addresses hardware random failures and systematic failures, it is also crucial to consider cybersecurity and safety of intended functionality (SOTIF). In this keynote, well cover NVIDIAs vision for functional safety, as well as our work with various international governing standards and regulations. The talk will also include an overview of the standard IEEE P2851, which aims to provide an exchangeable and interoperable format for safety analysis and safety verification activities at IP, SoC and system levels.The standard addresses interoperability challenges of dependable systems covering functional safety, SOTIF, cybersecurity and other characteristics such as reliability, maintainability and real time.

Presenter
Riccardo Mariani

NVIDIA

Presenter
Jyotika Athavale

Senior Functional Safety Architect, NVIDIA

11:00 AM - 11:25 AM

Optimizing EDA Workloads for SAFE-CDP A Novel Virtual Chip Design Environment on the Cloud

Track: Cloud

Ever increasing design size and complex technology requirement in advanced process nodes drive the demand for huge computing power in latest SOC designs to meet tight time-to-market requirement. Cloud now becomes a MUST. To provide shortest path to the cloud for our customers, Samsung Foundry has been working with cloud partners on SAFE(Samsung Advanced Foundry Ecosystem) and come up with SAFE-CDP(SAFE Cloud Design Platform), a virtual chip design environment on the cloud. SAFE-CDP has all things needed for cloud-based design and we went even further by running extensive experiments on the cloud to optimize EDA workload for the cloud. In this presentation, we provide our practice of building up a cloud-friendly environment for Synopsys IC Validator and Finesim by utilizing elastic CPU technology and GPU-based acceleration, respectively.

Presenter(s)
Taeil Kim

Samsung Electronics

11:00 AM - 11:25 AM

Update on Hardware Computing Technology and its Impact on Simulation

Track: Custom - AMS

Simulation rely on advance parallel computing technologies to improve performance, in this presentation, we will review the latest trend and update on hardware and its impact on simulation performance.

Presenter(s)
George Kokai

NVIDIA

11:00 AM - 11:25 AM

Getting the Most out of Fusion Compiler with RM 2.0

Track: Digital Design

Fusion Compiler RM 2.0 provides a quick and easy path to deploying best-in-class, R&D recommended technologies and methodologies for your Fusion Compiler design flow. Hit the ground running and stay up to date by using RM2.0. This talk will go through a brief overview of RM 2.0, its optimal configuration, and its intuitive use to get excellent out-of-the-box results. We will additionally share some results on real-world designs. how it’s setup, how to use it to get very good out of the box results, and provide some results on real world designs.

Presenter(s)
Stephen Oetting

Synopsys

11:25 AM - 11:50 AM

*The Next Level of Fusion: Fusion Technology + EMLL + Design Services

Track: Digital Design

Google designs specialized hardware for Machine Learning applications and has traditionally used a model based on Netlist Hand-off to IDMs (Integrated Device Manufacturers). This approach has limited Google’s control over PPA (Performance, Power and Area) of the design. To achieve greater PPA, Google decided to build an in-house Physical Design capability and partnered with Synopsys to do so. This presentation will highlight the many ways in which our multi-faceted partnership with Synopsys helped us push the PPA envelope and set us up for future success.

Presenter(s)
Venkata Rajesh Mekala

Google

Presenter(s)
Hiral Shah

Synopsys

11:00 AM - 11:25 AM

*Achieving 2-3X Execution Throughput Improvement using Zebu Latest Features and Design Optimization Techniques

Track: Emulation

Meeting TTM Schedules using faster execution of SoC Validation Milestones is a challenge in Validation world. A minimal of ~2x execution throughput improvement was required. This presentation discusses the Emulation flow that has helped in achieving the above goal while keeping the same Emulation Platform as well as Emulation Collateral and Test content. The flow also describes the latest and greatest versions of the Zebu software and new feature set available to achieve better zTime numbers. Various optimization techniques like DFT Scan portion optimization done in the flow to fit the design in specified capacity are also covered. The presentation describes the advantages of moving to the latest tool versions (2020.03-1) and different UTF Options tried. We also go into details about the DFT Tie-offs done for design optimization to efficiently manage resource utilization. We discuss specific build, compile and runtime flow changes required.

Presenter(s)
Umang Sharma

NXP

Presenter(s)
Mahendra Pratap Singh

NXP

11:00 AM - 11:25 AM

Billion Gates Power Analysis Using Emulation

Track: Low Power Design

This presentation will explain why looking at power analysis holistically using workloads running on the full SoC opens new opportunities for design teams to increase competitiveness of their products and reduce project risk. We will introduce breakthrough emulation technology that enable multiple analysis iterations per day.

Presenter(s)
Alexander Wakefield

Synopsys

11:00 AM - 11:25 AM

Integrated Development Environment (IDE) with SystemVerilog On-the-Fly Checks

Track: New Verification Technologies

Introducing Euclide - IDE with On-the-fly Design and Testbench checks highlighting integration with Verdi, VCS and ZeBu for improved productivity, performance and compatibility.

Presenter(s)
Eldon Nelson

Verification Application Engineer, Synopsys

11:00 AM - 11:25 AM

IC Validator Based Physical Verification Methodology for High Full Flow Productivity

Track: Physical Verification

With increasing DRC complexity at 7nm and large design sizes, physical verification turnaround time has become a key challenge to deliver tape-outs on schedule. In this presentation, Achnonix discusses physical verification methodology with IC Validator and how this methodology was successfully deployed on latest designs to enhance full flow productivity and accelerate design closure.

Presenter(s)
Namit Varma

Achronix

11:00 AM - 11:25 AM

Challenges and Approaches to Secure Hardware Design

Track: Secure, Safe & Reliable

Security hardening during the design creation flow has traditionally been very challenging. Every design group seems to have a unique flow, and every application has differing security requirements. These factors often drive increases in the power and area and decreases in the performance of the integrated circuit. There are multiple threats and many types of defenses already existing and new threats coming daily. How can developers expose and mitigate vulnerabilities during design creation while still considering competing design requirements? What steps are necessary early in the design flow to ensure proper chip provenance, authentication, provisioning, test, debug, and threat detection post tape-out? This tutorial presents how Synopsys, under a DARPA-sponsored program, is addressing these challenges.

Presenter(s)
Dale Donchin

Senior Program Manager, Synopsys

11:00 AM - 11:25 AM

50% Reduction in TAT Using Signoff-driven ECO Closure

Track: Signoff I

ECO closure is a major bottleneck for design closure and can result in tapeout delays due to the unpredictable nature of late stage ECO changes during the signoff stage of the design. In this presentation we will share a methodology and practical results of how we reduced of our ECO closure cycle by 50% by deploying Synopsys’ signoff-driven ECO closure solution.

Presenter(s)
Cheoljun Bae

Samsung Electronics

11:00 AM - 11:25 AM

Unified Library Characterization and Validation Solution Targeting Advanced Nodes

Track: Signoff II

High Performance, High Accuracy, High Reliability are the corner stones of lower technology node characterizations and libraries are the solid base of any successful chip tapeout. With our new Next generation Characterization Product we aim to achieve all of these goals and then some more. Next Generation Product is fully backward compatible with SiliconSmart ADV thus offering a seamless path to upgrade and also embeds the support for Next Generation simulator product. This tutorial will take you through the introduction of Next Generation of characterization product, all its current new offerings and an exciting roadmap of the upcoming features.

Presenter(s)
Fazela Vohra

Sr. Manager Applications Engineering, Synopsys

11:00 AM - 11:25 AM

*A Hybrid ATPG and Logic BIST Architecture for Extreme Compression

Track: Silicon Test and Analytics

Design-for-test solutions need increased capabilities as device complexity increases and semiconductor integration changes. Large complex devices at advanced process nodes require more rigorous testing methods and more test content. Test compression provides a method to deliver more test content through a limited number of tester channels. Using a hybrid system that supports deterministic test pattern generation and pseudorandom pattern application it is possible to make better tradeoffs between coverage, test data, and test time. The combination of TestMAX DFT and TestMAX XLBIST comprises the hybrid solution that scales to support testing over a range of different access methods from low pin count test access port (JTAG) to wide input/output connections. It reduces test time by supporting the delivery of fast external data and match internal scan speed to higher I/O speed.

Presenter(s)
Jon Colburn

NVIDIA

11:00 AM - 11:25 AM

*Efficiently Solving the Challenges of Clock and Reset Domain Crossing Verification for Large SoCs

Track: Static Verification

This presentation discusses the CDC/RDC verification approach that was undertaken using the VC SpyGlass CDC/RDC and the native SpyGlass tools. Various techniques used for addressing the runtime, noise reduction and violation clustering are presented. We will also discuss the various issues that were addressed in the SoC much earlier in the design cycle that would have been typically unfeasible in prior SoCs.

Presenter(s)
Francis Chockalingam

Broadcom

11:00 AM - 11:25 AM

*Delta-cycle Glitch Caught by Specific GUI Tool Selection

Track: VCS/Verdi/VIP

This presentation describes the difference in simulation behavior observations when a compiled database being simulated with different selections of GUI tool. We will discuss ways to dump and expand delta-cycle waveforms for analysis. The presentation will wrap up with a narration of how the observation being root caused to a race condition.

Presenter(s)
Yi Charn Goh

Intel

11:25 AM - 11:50 AM

*AI Based Design: Challenges and Methodology for Best PPA

Track: Artificial Intelligence

AI specific IP is becoming a must-have for many SoCs, however, due to the complex connectivity, IPs can easily be implemented in an inefficient manner. It is essential for designers to use many advanced analysis and implementation techniques to ensure their designs do not consume more than their assigned power and area budget. Designers must trial all available design techniques and, on occasion, think beyond what the tool has provided. This presentation will discusss each of the three levels of hierarchy and the challenges in the design.

Presenter(s)
Suraj Nair

Intel

11:25 AM - 11:50 AM

*Migrating VLSI Infrastructure to AWS - Challenge Accepted

Track: Cloud

While most of the web-based applications, AI developers and other computing resources users are migrating to the cloud, the EDA industry is not yet doing so in large quantities. Celeno, a world leader in wifi solutions, decided to harness the opportunities offered by the cloud, and migrated its entire Synopsys based RTL development and verification process to AWS. In this presentation, we will discuss best practices of the migration process, and will present a comparison of our previous solution vs. AWS in terms of stability, maintainability and performance. Migration challenges and our planned steps will also be discussed.

Presenter(s)
Zohar Tal

Verification Engineer, Celeno

11:25 AM - 11:50 AM

Discover Methods to Significantly Improve Performance on AMS Design

Track: Custom - AMS

Design and verify advanced AMS Design IP require fast simulation performance, this session will discuss a new approach to dramatically improvement simulation run time.

Presenter(s)
Kihoon Kim

Samsung Electronics

11:25 AM - 11:50 AM

Fast Forward Your Software Development with Advanaced Hybrid Technologies

Track: Emulation

Hybrid technologies have shown over the last few years, that they deliver signficant benefits for pre-silicon software bring-up. We will explain why hybrid has become an essential technology and how far the technology has advanced.

Presenter(s)
Varun Agrawal

Synopsys

11:25 AM - 11:50 AM

SAM Based Full Chip Multi-Voltage Verification in VC LP

Track: Low Power Design

Instance count in the netlist of full chip Graphics IP has increased exponentially in recent programs, posing roadblocks in Multi-Voltage (MV) Verification Signoff. At the same time, tighter schedules have required design teams to reduce iterations and time available for verifying the design. A full-blown chip level netlist either does not load into the VC LP tool or offers unreasonable verification run times. Black-boxing ‘placed and routed’ blocks in the netlist leads to critical verification coverage losses, creating a need for scripted checks thereby resulting in a delayed and low-confidence MV sign-off. This article discusses a Static Abstract Modelling (SAM) based chip level MV Verification using VC LP, that successfully enables handling the large size of the design (no tool capacity issues), without compromising MV sign off quality. The feature is based on retaining only the necessary logic gates and connectivity, required for verification, within the chip level netlist. Using SAM in VC LP, we were able to demonstrate at least a 3 week faster and highly reliable MV sign off. In our tests, SAM based VC LP simultaneously achieves increased verification coverage by up to 9% w.r.t our baseline runs, eliminates the need for any external MV checks and improves debug-efficiency by at least 25%. SAM based methodology is now and will be the new norm in MV verification especially for growing designs.

Presenter(s)
Balaji Vishwanath Krishnamurthy

Intel

11:25 AM - 11:50 AM

AI-powered Efficient Debug with Verdi

Track: New Verification Technologies

Regression Debug Automation (RDA) provides root cause analysis solutions for different types of errors (TB, DUT, VIP, IP, SoC) in the verification flow (check-in probe, regression, VCS version migration, design verification, and more). RDA categorizes failure types, applies diverse root cause analysis engines then generates an RCA report for users to easily understand and manage it. RDA automates the debug flow for design errors and can improve the performance of design verification dramatically.

Presenter(s)
Nasser Lin

Synopsys

11:25 AM - 11:50 AM

*Full Chip Antenna DRC Runtime Challenges and Solutions

Track: Physical Verification

Full chip antenna violations was one of the critical challenge in the last stretch our project. Full chip antenna checks are always late in the stage due to the nature of the checks. In the usual design flow, full chip antenna checks required LVS and partitions level antenna checks clean in order to detect the inter-partition violations. In order to reduce inter-partition violations and able to iterate full chip layout verification in much faster way, drc_check_ant_diode flow, a method for pushing down full chip level related antenna violations to partitions and virtual subsystem creation is developed. The proposed methodology reduced the inter-partition antenna violations in second milestone, enabled early detection of the inter-partition antenna violations at full chip level and resolved it earlier without the needs to wait for full chip layout verification iteration results.

Presenter(s)
Sie Ang Wong

Structure Design Engineer, Intel

11:25 AM - 11:50 AM

A Robust Flow for Recreating Obsolete Components Using FPGAs

Track: Secure, Safe & Reliable

Some custom VLSI technology is approaching 40 years of age. End of life buys and obsolete technology or destroyed mask sets may make buying new parts impossible. Luckily, FPGA technology has become more affordable, faster and large enough to reproduce most VLSI designs or even boards from 20+ years ago. In this paper Ill introduce a flow for re-implementing a legacy design in an FPGA.

Presenter(s)
Frank Bruno

FPGA Engineer, ASIC Solutions

11:25 AM - 11:50 AM

*Next Big Break Through in Optimization Arena

Track: Signoff I

Power, Performance and Area (PPA) are the main key areas of focus in current SoC design. Signoff based optimization for Power, Timing and ERC cleanup has been proven as key element during design cycle. Conventional signoff based optimization solutions till now only try to predict and estimate impact of changes on physical implementation. The misalignment between predictability and actual implementation are often the root cause to a long ECO loops for design convergence.

New presented tool takes innovative approach and make the implementation as integrated part of optimization. Based on this new approach, optimization flow can take the advantage and automatically resolve any fallout and converge the design. Comparison between traditional design flow to presented integration solution achieved 3x to 5x reduction in optimization cycle convergence and enable better QOR. In addition, it also delivers the opportunities to develop new methods and algorithms to further improve design QOR.

Presenter(s)
Amir Yashfe

Intel

11:25 AM - 11:50 AM

*Migrating to Fusion Compiler™ from Design Compiler, Design-for-Test & IC Compiler II Has Never Been so Easy!

Track: Silicon Test and Analytics

A presentation about the benefits of using Fusion Compiler™ over the traditional Synopsys tools like Design Compiler, Design for Test and IC Compiler II.

Advantages like shorter run-times, better performance, easy Design for Test integration, higher utilization, reduction in total area, and more will be given as examples. Besides the advantages of using one platform that combines and contains all the toolsets, what makes it more productive to the end-user is the inner integration level between those individual tools when they are grouped under Fusion Compiler. Also, how in Microsoft the switch to Fusion Compiler, under a very demanding and stressful timeline was gone smoothly while meeting the due date even before expectations. Emphasizing that following the reference manual and using the automatic conversion scripts short the ramp-up time compared to a full end to end flow bring up from scratch.

Presenter(s)
Aviad Ben-Haim

Microsoft

11:25 AM - 11:50 AM

*Metastability Bugs Prevention via CDC and RDC Verification: Learnings from SoC Design

Track: Static Verification

Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) verification are important front-end RTL static checks for uncovering metastability bugs during early design phase. This presentation presents the CDC/RDC verification flow used by a System on Chip (SoC) design that has both proprietary IPs and industry standard off-the-self IPs. It shows how bottom-up hierarchical CDC/RDC verification with flat mode run has been implemented in catching metastability bugs that are caused by the integration of IPs from heterogenous IP providers. Each of these bugs is discussed in detailed in term of, how it has been caught in the flow and how it has been fixed. Catching metastability bugs caused by CDC/RDC violations prior to product tape-in would be the key to a successful product. It is anticipated that the learnings presented here could be beneficial to other SoC or subsystem that uses IP from heterogenous IP providers.

Presenter(s)
Lee Fueng Yap

Intel

11:25 AM - 11:50 AM

*UVM DUT Harness Verification Technique…Minus the Harness!

Track: VCS/Verdi/VIP

In 2011, David Larson authored a paper entitled, UVM Harness Whitepaper - The missing link in interface connectivity [1]. The paper described an advanced technique to connect an interface to a DUT with a reusable harness technique. This presentation describes an easier way to connect to the dut_if to the DUT, using the harness technique, but without the harness! We have discovered a way to remove the intermediate harness requirement and simplify the DUT-dut_if connection by adding a set-method inside of the dut_if itself, where the method hierarchically can be called to store the dut_if handle into the uvm_config_db. The dut_if file not only includes the dut_if description with set-method enclosed within the interface definition, but it also includes a separate bind_dut_if() module that does the binding of the dut_if to the DUT itself. The advantages and simplifications that this non-harness technique enables are described in this presentation.

Presenter(s)
Clifford Cummings

Sunburst Design

12:00 PM - 12:25 PM

*Edge AI Inference SoC Physical Design Challenges & Methodology to Achieve Best PPA

Track: Artificial Intelligence

Edge computing is no more a dream, reality of today and a necessity in future; from the consumer products to far end server with different scale. An AI Edge inference accelerator offloads ML specific loads from server and does computation in a much better, energy effecient way, with help of power architecture focused on saving every mW. In addition, a complex larger SoC in N6 technology node with many power domains focused on getting the best TOPS/W, has greater challenges from synthesis to timing closure. The focus of this presentation is on the methodology & approach on how we dealt with those challenges to achieve best PPA. We will discuss in detail on how Auto Macro Placement strategies, CCD everywhere, auto density control with incr clock opt, enabling signoff tool capability while PnR & other methodologies have helped improve std cell utilization, SVT, and timing.

Presenter(s)
Dhanapathy Krishnamoorthy

Intel

12:00 PM - 12:25 PM

Replay: CNN Acceleration: A Short Road Trip

Track: Automotive

Convolutional Neural Networks (CNN) are widely adopted for various computer vision tasks. They are also gaining traction in the auto-motive industry. As such, front-view cameras may rely on CNNs for semantic segmentation and object detection. They typically require very performant and very efficient CNN accelerators. The presentation will give a brief overview of CNNs in general. It will explain the use of CNNs for semantic segmentation and object detection and describe some CNNs designed for these tasks. It will discuss the challenges of embedding a CNN accelerator in a SoC and of providing a SW tool chain that enables the full performance and efficiency of the CNN accelerator. It will describe the performance results generated by Bosch using Synopsys' DesignWare ARC EV processor and CNN engine with 3520 MACs.

Presenter(s)
Filip Moerman

System Architect, Bosch

12:00 PM - 12:25 PM

Scaling DSO.ai on Microsoft Azure

Track: Cloud

When designing advanced silicon ICs, design teams are faced with a massive search problem, needing to iteratively take many layers of decisions in a complex environment. Working with Microsoft Azure, Synopsys has demonstrated how DSO.ai can leverage available compute on the cloud to dynamically and flexibly scale the exploration of choices in physical design. In this session, we will present the DSO.ai Cloud environment and demonstrate the benefits of running the world’s first AI application for chip design – on Microsoft Azure.

Presenter(s)
Prashant Varshney

Microsoft

Presenter(s)
Benoit Claudel

Synopsys

12:00 PM - 12:25 PM

Flexible and Feature Rich Simulation Cockpit for Netlist

Track: Custom - AMS

There are many solutions in the market for schematic based simulation environment, but none for Netlist. Synopsys Cockpit fills this gap and is Flexible and Feature Rich. The tool helps analog and mixed signal design engineer to run simulations in a very interactive way reducing manual errors and its tight integration with waveform and calculator tool makes debug very easy. The Tool also has a rich collection of tcl APIs making it possible to integrate any Internal Tools, Data mine your design and perform other complicated tasks. This presentation will go over the key reasons why we had to pick a Netlist based solution, How we were able to leverage the tcl APIs and automate key tasks to boost productivity of design engineers.

Presenter(s)
Om Johari

Intel

12:00 PM - 12:50 PM

Achieving the Best PPA on Advanced Arm® Cores with Synopsys’ Fusion Design Platform

Track: Digital Design

In this session, Arm and Synopsys experts will highlight the best practices, new methodologies, and co-developed enabling technologies that deliver the industry's leading power, performance, and area (PPA) for the latest Arm cores, targeted for smartphones, laptops, hyper-scale cloud computing, 5G infrastructure, and beyond. These key technologies include physically-aware RTL restructuring with RTL Architect, signoff-driven ECO closure leveraging PrimeECO™, In-Design power-integrity analysis and fixing through RedHawk Analysis Fusion, balanced H-Trees as part of an efficient MSCTS implementation, hierarchical Arm-core design, and placement-attractions methodologies.

Presenter(s)
Pierre-Alexandre Bou-Ach

Arm, Senior Manager

Presenter(s)
Shankar Vellanthurai

Technical Staff, Synopsys

Presenter(s)
Gary Rudolph

Staff Application Engineer, Synopsys

12:00 PM - 12:25 PM

*Optimizing Firmware Performance of an NVMe-based SSD on Zebu Hardware Emulation Platform

Track: Emulation

This presentation explores the details of the Synopsys Zebu emulation platform coupled with the PCIe virtual host solution for pre-silicon NVMe device controller validation and firmware latency measurements. This integration provides a complete solution for firmware developers to measure cycle accurate performance numbers on a full virtual platform early in the product development cycle.

Presenter(s)
Sangeetha Chandran Sarala

Micron Technology

Presenter(s)
Johnny Li

Micron Technology

12:00 PM - 12:25 PM

The New AI Frontier – Breaking Down Power Barriers

Track: Low Power Design

A huge number of new AI architectures have been implemented in silicon by now. Every architecture strived for best AI algorithm throughput. Emulation was used as the key verification technology to get the brand new AI software stacks and architectures working pre-silicon. Now it is time for the second wave of AI innovation: Delivering on the promise of lowest power consumption measured in tera operations per Watt (TOPS/W). In this session we describe the low power design flow and emulation based power verification with ZeBu Empower. We will share specific results obtained from real life AI designs to illustrate how design teams can get to the most differentiated and optimized AI architecture.

Presenter(s)
Zohreh Azizi

SiMa.ai

12:00 PM - 12:25 PM

Driving Efficiency & Productivity in SoC Verification Sign-off with Unified Verification Management Automation

Track: New Verification Technologies

This presentation is on improving verification productivity by unifying and automating Verification Continuum flows. We will show the latest advancements and results from the natively integrated VC Execution Manager solution.

Presenter(s)
Kirankumar Karanam

Synopsys

12:00 PM - 12:25 PM

*Secure Lynx-Based Cloud Design Environment Enabling Accurate and Efficient Physical Verification and Fabrication Sign-Off

Track: Physical Verification

We present a secure, automated Cloud Design Environment (CDE) based on Lynx Design System and fully operated in a cloud computing system. We use Lynx to generate libraries of essential parameters such as physical layer, CAD layer, and runsets information. Integrating a parameter library and a configurable setup file, we enable a series of design sanity checks and physical verification checks, utilizing IC Workbench and IC Validator. We show the CDE to select the runsets required by the foundry, based on a design file and user inputs. The entire flow is executed within the Amazon Web Services (AWS) GovCloud. We demonstrate the design configuration libraries and the relevant physical verification capabilities achieving gold standard accuracy and enhancements in individual flow runtime and overall productivity. We apply the CDE across FinFET and bulk nodes for an extensive list of products including High-Performance Computing, Mobile, Automotive, and IoT for fabrication tapeout signoff.

Presenter(s)
Lifu Chang

Director, The MOSIS Service

12:00 PM - 12:25 PM

A Framework for Assessing the Vulnerability of ICs Against Fault Injection Attacks

Track: Secure, Safe & Reliable

Fault-injection attacks have become a major concern for hardware designs, primarily due to their powerful capability in tampering with critical locations in a device to cause violation of its integrity, confidentiality, and availability. Researchers have proposed a number of physical and architectural countermeasures against fault-injection attacks; however, these techniques usually come with large overhead and design efforts making them difficult to use in practice. In addition, the current electronic design automation (EDA) tools are not fully equipped to support vulnerability assessment against fault-injection attacks at the design-time to avoid tedious manual design review. In this paper, we propose an automated framework for fault-injection vulnerability assessment of designs at gate-level using Synopsys Z01X, while considering the design-specific security properties using novel models and metrics. Our experimental results on the security properties of AES, RSA, and SHA implementations show that the security threat from fault-injection attacks can be significantly mitigated by protecting the identified critical locations, which are less than 0.6% of the design.

Presenter(s)
Huanyu Wang

Research Assistant, University of Florida

12:00 PM - 12:25 PM

New Pattern Conversion Technology

Track: Silicon Test and Analytics

Intel is working to replace an internally developed CPU-centric pattern conversion methodology with a more streamlined approach with a widely adopted third-party tool while still meeting the needs of different business segments. Intel partnered with an EDA vendor to drive enhancements to the pattern conversion methodology as well as is managing total cost of ownership. This allowed for standardization and simplified conversion of STIL patterns. The new pattern conversion methodology with specific customization maintained the requirement for high volume manufacturing within Intel's ecosystem.

Presenter(s)
Pallav Gupta

Software Engineer, Intel

12:00 PM - 12:25 PM

*Scalable RDC Signoff Methodology for Large SoCs

Track: Static Verification

Reset Domain Crossing (RDC) has emerged as critical issues in the last few years. Previously, resetting of systems happened at power up, with a handful of reset signals, and a reset sequence for a few thousand cycles. In today’s Low-Power, High performance SoCs, multitudes of resets, power domains and software generated resets have added complexity to the overall RDC verification, which, unlike CDC, is not limited to the asynchronous clock domains. For this reason typical RDC paths are in the order of tens of thousands or more for SoCs. Since software and power domains resets need to be applied very frequently on the parts of the design, correct reset design has become very critical. Wrong reset sequencing can not only cause meta-stability, it can lead to unknown values propagating through the system, causing unexpected behavior compromising the security of the system. In this presentation, we will highlight the unique RDC methodology using VC SpyGlass which helped us sign off RDC effectively at RTL without waiting for GLS or actual silicon. in addition, we will focus on Verdi based RDC aware debug, grouping and filtering which helped improve overall turnaround time significantly.

Presenter(s)
Ray Wu

Marvell

12:00 PM - 12:25 PM

Catching Bugs early with Dynamic Simulation

Track: VCS/Verdi/VIP

See VCS's new "Dynamic Multi-cycle path Verification" to catch bugs at RTL and performance improvements with "Dynamic Test Loading" and "Distributed Compile" capabiltiies.

Presenter(s)
Arti Gupta

Synopsys

Presenter(s)
Mary Thomas

Synopsys

12:25 PM - 12:50 PM

Case Study for AI SoC IP: Emerging Neural Networks Drive Innovation

Track: Artificial Intelligence

The demand for neural network processing is requiring SoC hardware innovation across all market segments. These demands bring a new set of IP requirements unique to different segments, including new processors, higher bandwidth memories, high speed interconnect, and optimized architectural configurations. Constantly evolving next-generation neural networks place unique additional demands over and above the standard PPA needs of traditional chipset hardware. This presentation will describe how a leading AI SoC customer supports emerging requirements for fast-changing neural networks. Attendees will learn about successful implementations of how IP, IP tools, and design services can enable more competitive, higher performance SoC designs while minimizing time-to-market.

Presenter(s)
Ron Lowman

Product Marketing Manager, Synopsys

12:25 PM - 12:50 PM

Replay: Accelerate the Development of Dependable Automotive SoCs with Synopsys' Comprehensive Safety-Aware Solution

Track: Automotive

At higher levels of autonomy, the autonomous driving (AD) compute solution will become more centralized to rapidly fuse multimodal sensor data and safely choose and initiate self-driving actions. Complex automotive SoCs with purpose-built processors to increase computational efficiency require automotive-grade IP and ISO 26262-certified safety-aware design and hardware and software verification solutions to meet strict design targets to achieve target ASIL. Before silicon is available, early development and testing of safe and secure software relies on virtualized hardware. Synopsys partners with automotive market leaders and new entrants to accelerate development of safety-critical SoC. In this session, we present Synopsys safety-aware expertise, IP and tool solution to help reduce cost, alleviate risk and accelerate go-to-market.

Presenter(s)
Stewart Williams

Senior Automotive Vertical Marketing Manager, Synopsys

12:25 PM - 12:50 PM

Design Migration and Simulation Challenges Getting Resolved in Enabling Custom Compiler for 7nm Platform

Track: Custom-AMS

Design data migration between different nodes is a challenging task. It becomes even more difficult when stackMos devices are present in the design. In this paper we talk about the productivity enhancement achieved using the Custom Compiler design platform, starting right from schematic migration until simulation. The command line simulation challenges have been resolved by the simulation environment with the enablement of Multi test-bench and Sequential test-bench features. Handling measurement expressions effectively provides a faster turnaround time. The test bench reusability feature saved considerable time during design/spec changes, and saving simulation history provides a better way to preserve and milestone the simulation database.

Presenter(s)
Danish Shaikh

Western Digital

12:25 PM - 12:50 PM

*Pre-Silicon Functional and Power Validation Using Gate-Level Emulation

Track: Low Power Design

Netlist/gate level validation is an important part of Pre-silicon validation. Gate level simulation (GLS) is traditionally used for functional and X-prop validation. On a very large design, GLS requires lots of compute memory, functional tests run very slow, and it's not feasible to run real driver workloads. In this presentation, we will discuss how we use Gate Level Emulation for significantly faster runtime (1000X) and to run driver workloads to measure power (average/dynamic) with high accuracy which is important for signoff.

Presenter(s)
Ameya Rane

Intel

12:25 PM - 12:50 PM

High Performance Layout Analysis with IC Validator Workbench

Track: Physical Verification

IC Validator Workbench is a must-have utility for IC Validator physical verification flow. It enables efficient viewing and editing of Layout databases: Quickly open layout database and access the graphical data for fast review and editing, Compare Layout databases, Automate repetitive tasks using standard scripting languages (Tcl or Python). IC Validator Workbench can also be used to efficiently merge multiple database files into your complete design for chip finishing.Additionally, the full array of IC Validator tools are integrated and accessible in IC Validator Workbench environment to make design verification easy to accomplish.

Presenter(s)
Peter Thwaite

IC Validator Applications Engineer, Synopsys

12:25 PM - 12:50 PM

DoD State-of-the-Art Enterprise Hardware Emulation

Track: Secure, Safe & Reliable

The microelectronics landscape is rapidly changing for the DoD, as integrated circuit and system design complexities and hardware assurance requirements increase owing to high-performance mission critical requirements and the need to protect sensitive data. The DoD data center has unique requirements uncommon to the commercial world. Corporate suppliers deal primarily with relatively static projects for hardware emulation configuration before switching to a new project and new data center configuration. The low project/configuration change velocity is a benefit for corporate solutions that the DoD heterogeneous user/project base cannot leverage. The successful DoD data center must address the more complicated challenges associated with a very high change velocity. This atypical aggressive use model delivers the DoD significant economic advantages, though at the expense of up-front implementation cost. For current and future DoD requirements, this paper outlines decisions and processes that will provide the DoD with improved performance and higher reliability at lower cost than current best practices allow.

Keywords: Trust, Enterprise, Data center, Simulation Acceleration, Hardware Emulation, Verification, Hardware Assurance

Presenter(s)
Dr. Christopher Diltz

Edaptive

12:00 PM - 12:25 PM

Estimating DVD-Induced Timing Impact Using PrimeTime® and RedHawk-SC

Track: Signoff I

In this work, PrimeTime's new DVD analysis has been proved. The new method of PrimeTime is able to directly read Redhawk-SC's DVD report and estimate its impact on timing. It is shown that the new method is well correlated with quad-core ARM CA53 chip implemented in Samsung's LN10LPP process.

Presenter(s)
Jongyoon Jung

Staff Engineer, Samsung Electronics

12:25 PM - 12:50 PM

PrimeTime® Technologies for Designers' Productivity

Track: Signoff I

Dramatic rise in design size and complexity has lead to a slew of signoff challenges that affect designers ability to meet TAT target. In this tutorial, major advances in PrimeTime to address these challenges will be reviewed. We will cover new techniques to improve productivity, such as reducing report runtime bottlenecks, managing number of corners in multivoltage design, and reducing runtime & memory requirement for hierarchical designs.

Presenter(s)
Arundas Haridas

Manager I, Synopsys

12:25 PM - 12:50 PM

Fusion of Next-Generation RTL-to-GDSII Solutions and State-of-the-Art DFT Technology

Track: Silicon Test and Analytics

Power management for thermal requirements is the most important design challenge not only for mobile applications but also for server applications. A convergent RTL-to-GDSII flow is critical to meet the two opposing requirements of high performance and low power consumption within competitive time-to-market goals. Furthermore, to carry out sufficient tests in a short time with a limited number of pins, an integrated, state-of-the-art DFT technology is highly desired. In this session, we will discuss our efforts in building an integrated flow using Fusion Compiler, which realizes a highly-convergent singular design flow from RTL-to-GDSII, including DFTMAX scan compression technology, and share the results of our application on high-performance controller designs for NAND flash and SSD.

Presenter(s)
Yusuke Takahashi

Kioxia

12:25 PM - 12:50 PM

*The Latest Advancements in Preventing Reset Domain Crossings Bugs

Track: Static Verification

Recently, Reset Domain Crossings (RDC), CDC’s lesser-known twin, are gaining widespread recognition across the industry. In an RDC, the asynchronous assertion of a transmit flop’s reset can cause an input change at the receiver’s flop that violates setup/hold timing requirements, resulting in metastability. Mature RDC RTL static-checking tools and flows are now available, and many design teams have introduced them as an important part of their RTL verification flow. This presentation will discuss the latest approaches for resolving RDC issues, the new methodologies for detecting them, and the improvements in runtime and capacity that a new generation of RDC static tools can provide.

Presenter(s)
 Joseph Mirsky

Intel

12:25 PM - 12:50 PM

Powerful Debug of Complex Constraints during VCS Simulation

Track: VCS/Verdi/VIP

Learn about how to use Interactive Verdi with VCS solver engine and debug complex constraint failures.

Presenter(s)
Jason Chen

Synopsys

Presenter(s)
Rajatha Kashyap

Synopsys

1:00 PM - 1:25 PM

Ensuring Functional Safety of Memory IP Using TestMAX CustomFault

Track: Custom - AMS

Memory real estate is continuously increasing, reaching more than 80% on present day SoCs. In Automotive SoCs, Memory IPs are used for various applications ranging from ADAS to navigation and infotainment. SoCs designed for life critical applications like ADAS (ASIL-D category in ISO26262 standard) go through rigorous functional safety checks and FMEDA (Failure Modes, Effects and Defect Analysis) becomes a necessary step to systematically predict the failure rate of all IPs used in such subsystems. Among various objectives of FMEDA, we will focus on the requirement for fault analysis and discuss how we are able to use TestMAX CustomFault to perform fault analysis to ensure functional safety of our embedded Memory IPs catering to the Automotive market.

Presenter(s)
Kedar Janardan Dhori

Principal Engineer - Member Tech Staff, STMicroelectronics

1:00 PM - 1:50 PM

Secure Semiconductor Development - Design Challenges and Reasonable Practices

Track: Secure, Safe & Reliable

This talk will address where common vulnerabilities are introduced during the design of an SoC, how good practice can help security assurance when designing logic, integrating IPs or performing pre-silicon verification.

Presenter(s)
Jean-Philippe Martin

Security Lead, Intel

1:25 PM - 1:50 PM

Using HSPICE StatEye and IBIS-AMI models for LPDDR5 SI Analysis’

Track: Custom-AMS

As chip and board speeds continue to increase, new design and verification challenges emerge. HSPICE reveals signal integrity problems caused by jitter, crosstalk, ringing, ground bounce, and other noise sources. With extensive model and element support, HSPICE is the ideal simulator that can satisfy your silicon-to-package-to-board-to-backplane SI simulation needs. In this work, we will present a practical user case of Micron on how they utilized the advanced elements, comprehensive multi-domain analysis and cutting-edge StatEye analysis with IBIS-AMI models offered by HSPICE to accomplish the challenging LPDDR5 SI Analysis. Two example simulations -DQ0, single line, 4000 bit PRBs stimulus and DQ7, full channel with crosstalk - are provided.

Presenter(s)
Randy Wolff

Micron

7:00 AM - 7:50 AM

Facilitating Distributed Development of Safety Critical Automotive IP and SoC

Track: Automotive

Standards such as ISO 26262 define strict requirements, processes, and methods that all stakeholders IP vendors, sub-system and SoC developers must abide by when designing safety critical automotive products. One such requirement is the Development Interface Agreement (DIA) which defines the interactions, interfaces, responsibilities, dependencies and work products to be exchanged between customers, like Infineon, and suppliers for all distributed safety related activities. In this session, we will explain the details of distributed development based on DIA and outline the different activities for which DIAs must be signed during a distributed development process. In the second part of the presentation, Infineon will highlight their approach on meeting SoC-level functional safety objectives while closely collaborating with Synopsys.

Presenter(s)
Vladimir Litovtchenko

Functional Safety Director, Synopsys

Presenter(s)
Dietmar Koenig

Infineon

8:00 AM - 8:25 AM

Ensuring Functional Safety of Memory IP Using TestMAX CustomFault

Track: Automotive

Memory real estate is continuously increasing, reaching more than 80% on present day SoCs. In Automotive SoCs, Memory IPs are used for various applications ranging from ADAS to navigation and infotainment. SoCs designed for life critical applications like ADAS (ASIL-D category in ISO26262 standard) go through rigorous functional safety checks and FMEDA (Failure Modes, Effects and Defect Analysis) becomes a necessary step to systematically predict the failure rate of all IPs used in such subsystems. Among various objectives of FMEDA, in this paper, we focus on the requirement for fault analysis and discuss how we are able to use TestMAX CustomFault to perform fault analysis to ensure functional safety of our embedded Memory IPs catering to the Automotive market.

Presenter(s)
Kedar Janardan Dhori

Principal Engineer - Member Tech Staff, STMicroelectronics

8:25 AM - 8:50 AM

Analog Fault Simulation for ISO 26262 Using TestMAX CustomFault

Track: Automotive

This presentation describes the application of the Synopsys analog fault simulator TestMAX CustomFault at TDK-Micronas. It gives an introduction to the tool, the methods used in it, and its application for the determination of some ISO26262 metrics.

Presenter(s)
Erich Gottlieb

Senior EDA Engineer, Micronas

9:10 AM - 9:50 AM

Architecting the Next 100B Intelligent Devices

Track: KEYNOTE

As the industry mobilizes to produce the first 100 billion high performance compute devices, it faces daunting new headwinds born at the intersection of systemic and scale complexity. From igniting neuromorphic AI in the cloud to deploying zetaflops of compute to the edge, award-winning innovator and Intel Fellow Becky Loop tackles a spectrum of the most current design challenges from IP reuse and dynamics shifts, to congested data flow and software/security compatibility issues.

Presenter(s)
Becky Loop

Fellow and Chief Architect, Memory, Intel

10:00 AM - 10:50 AM

Executive Panel: How is AI Changing the Way We Approach Chip Design?

Track: Artificial Intelligence

The semiconductor industry is entering a Cambrian era of innovation. A plethora of domain-specific architectures are heralded as the answer to overcoming the slowing of Moore’s Law – but can design teams scale? Can AI enable a path to 1,000X compute performance and energy efficiency? Our executive discussion panel of industry leaders will weigh-in on the promise of AI for chip design, drawing from real-world experiences.

Moderator
Stelios Diamantidis

Synopsys

Panelist
Artour Levin

Intel

Panelist
Paul Penzes

Qualcomm

Panelist
Sangyun Kim

Samsung Electronics

Panelist
Thomas Andersen

Synopsys

10:00 AM - 10:25 AM

Safety Critical Lint Methodology for Automotive Customer

Track: Automotive

Currently the automotive industry is going through a major transition and applications like self driving cars require enormous computing power which make designs more complex in nature. This change not only requires a faster but also exhaustive signoff for safety critical automotive designs. We consulted with automotive industry leaders and developed a safety critical methodology on proven SpyGlass Lint technology. This methodology has selected lint rules and custom settings devised specifically for automotive static signoff.

Presenter(s)
Rahul Chirania

Sr Staff Application Engineer, Synopsys

10:00 AM - 10:25 AM

Simulation Environment Update

Track: Custom-AMS

Modern Circuit designs require new ways of analysis and characterization. Learn how the Simulation Environment can solve these challenges.

Presenter
Samad Parekh

Synopsys

Presenter
Manu Velayudhan Pillai

Synopsys

10:00 AM - 10:50 AM

Simply Better RTL: Enabling Shift Left Strategy with RTL Architect

Track: Digital Design

This session will provide a closer look into RTL Architect's advanced technologies and share insights from lessons learned across multiple customer engagements over the past year. We will review and demonstrate how RTL Architect capabilities have enabled customers to improve and significantly speed up the complete RTL creation and refinement process. We will also discuss some insider tips and tricks when deploying RTL Architect.

Presenter(s)
Michael Montana

Synopsys

Presenter(s)
Jim Schultz

Synopsys

10:00 AM - 10:25 AM

*Enabling External Customer to use NXP’s In-House Zebu Emulation Setup to meet Pre-Silicon Verification Milestones

Track: Emulation

SoC validation faces constraints due to the unavailability of SoC Emulation Setup on the IP Vendor side. A hands-on availability of SoC Emulation setup at Third Party IP Vendor was required to meet Pre-Silicon Verification Milestones and Time-to-Market schedules. This presentation discusses the Emulation flow that has helped in achieving the above goal by enabling external customer/Third Party IP Vendor to run their test content onto NXP Project’s Emulation Builds. The flow also covers the integration effort and the Hardware setup required. This presentation discusses the re-use of verification APIs used by the external customers into our NXP Emulation flows, and mentions the Hardware setup changes needed, like multiplexing of CodeWarrior Tap and External Customer Debugger Connections using Smart ZICE Adaptor. We also discuss results of the test scenarios, and available Debug features & limitations, including how the verification test content can be leveraged for Validation of emulation models.

Presenter(s)
Umang Sharma

NXP

10:00 AM - 10:25 AM

Die-to-Die Connectivity - Trends, Use Cases, Requirements

Track: IP

The increasing volume of data for AI workloads is driving the need for more advanced networking functionality for faster data movement. SoCs for hyperscale data centers, artificial intelligence, and networking applications are more complex. Such SoCs are disaggregated in a multi-die package, requiring a robust and reliable 112G USR/XSR or HBI links to allow inter-die connectivity. In this session, we will describe the new use cases, such as co-package optics, for die-to-die connectivity as well as outline key design requirements of standards-based SerDes and parallel die-to-die interface solutions with testability and performance/power tradeoff capabilities and supporting interposer and substrate technologies for 2.5/3D packaging.

Presenter(s)
Manmeet Walia

Sr. Product Marketing Manager, Synopsys

10:00 AM - 10:50 AM

Panel: End to End Low Power Solution Panel

Track: Low Power Design

Advanced nodes, new AI architectures, and multi-voltage SoCs. What are your most daunting low power design challenges? Join us to hear what industry experts from Intel, Microsoft, and Google are saying about the factors driving complexity in low power design and the innovation needed to be successful.

Moderator
Renu Mehra

Synopsys

Panelist
TBD

TBD

Panelist
Chip Stratakos

Google

Panelist
William G. Crocco

Intel

Panelist
Anand Iyer

Microsoft

10:00 AM - 10:25 AM

Free PDK3: A Novel PDK for Physical Verification at the 3nm Node

Track: Physical Verification

To maintain aggressive scaling trends, current devices use track height reduction as the primary scaling knob. Gate All Around process technology offers a way to reduce track-height while using 90% or more of current FinFET process steps. To enable teaching and research, we have developed a predictive process design kit (PDK) in collaboration with Synopsys, targeted for the 3nm node. Cell layouts and schematics were designed using Synopsys Custom Compiler and verified using Synopsys IC Validator. We will discuss challenges encountered in design rule creation and DRC and LVS runset development. Some early results will be shown.

Presenter(s)
Rhett Davis

Department of ECE NC State University

10:00 AM - 10:25 AM

*Using PrimeShield Variation Analysis to Create a More Robust Core... at Fraction of the Cost of Flat Margins

Track: Signoff I

Technologies have increased variability content, either due to the natural increase of local mismatch with shrinking geometry, or with more traditional technologies going down in Vdd to support more advanced applications. In this presentation, we demonstrate the benefits of PrimeShield variation analysis to handle local mismatch impact with greater accuracy than standard LVF allows. Specifically, it enables the analysis of multiple paths in a true statistical fashion and to identify cells bottlenecks. PrimeShield variation aware ECO is used to increase the robustness of cpu cores at the fraction of the cost of a traditional - non variation aware - ECO with fixed margin. Finally, Fast MC analysis results are shown, enabling spice accuracy variation analysis in a fast and efficient fashion.

Presenter(s)
Marchal Sebastien

Principal Engineer - STA Expert, STMicroelectronics

10:00 AM - 10:25 AM

Efficient Simulation and EMIR Validation with StarRC GPD Flow

Track: Signoff II

Moving from an existing EDA tool to a new one is a nightmare due to the time it takes for synchronizing the database of new tool with existing flow. If we take the example of extraction database, it is used for post layout simulation and EMIR analysis. With the help of the new StarRC GPD based flow developed at ST Microelectronics we were able to simplify the flow and achieve efficiency gain. In this session we will showcase the seamless flow as adopted by ST and its benefits such as reduced disk space, improved TAT, etc.

Presenter(s)
Atul Bhargava

Principal Design Engineer, STMicroelectronics

10:00 AM - 10:25 AM

TestMAX Advisor ‐ Boost Coverage and Reduce Pattern Count Today!

Track: Silicon Test and Analytics

Test points are a well-known, but underutilized design-for-test technique to boost coverage and reduce the number of test patterns required to achieve fault coverage targets. This session will provide a brief tutorial on TestMAX Advisor to analyze RTL and gate-level designs to determine the most impactful control and observation points. Furthermore, unique fusion technology and its usage will be explained to implement test points in the design using methods that ensures optimal performance, power, and area (PPA) of the design. Learn how to easily deploy test points with a single step that automatically combines TestMAX Advisor testability analysis and TestMAX DFT design-for-test within Synopsys synthesis products to improve ATPG and logic BIST results today!

Presenter(s)
Raja Koneru

Synopsys

10:00 AM - 10:25 AM

*Noise Reduction using Static and Formal Aware Linting in a Single Phase

Track: Static Verification

This presentation will demonstrate the critical design structural and functional issues of ML based SoC designs and how we use VC SpyGlass Integrated static and functional lint flow to handle these design issues.

Presenter(s)
Saurabh Jain

SiMa.ai

Presenter(s)
Jazib Anwer

Synopsys

10:00 AM - 10:25 AM

Increase Coverage, Reduce TAT with VCS Intelligent Coverage Optimization -- Driving Verification Efficiency with AI/ML Innovation

Track: VCS/Verdi/VIP

See how VCS's new Intelligent Coverage Optimization and Dynamic Performance Optimization Technologies deliver unique ability to improve verification efficiency and productivity.

Presenter(s)
Will Chen

Synopsys

10:00 AM - 10:25 AM

VC Formal Seamless Scaling on AWS SOCA: A Winning Formula to Shift-Left Verification

Track: Cloud

Cloud provides a unique opportunity to get access to hundreds of cores. Moving EDA workloads to the cloud presents a unique set of challenges and considerations. In this presentation we will explore solutions to those challenges by demonstrating how to seamlessly scale Formal Verification using Scale-Out Computing on AWS (SOCA). VC Formal on AWS SOCA provides a unique solution to Shift-Left Verification with better performance & convergence.

Presenter(s)
Pratik Mahajan

Synopsys

Presenter(s)
Ahmed Elzeftawi

Amazon

10:00 AM - 10:25 AM

*Virtualized CPU Usage in SoC Verification

Track: Virtual Prototyping

The purpose of this work is to study virtualized CPU usage in SoC verification. A complete virtual CPU subsystem is implemented and used to study the performance and applications of a virtualized environment in top-level SoC design. In this work, a virtual fast model of ARM Cortex-A55 microarchitecture is used. It implements the ARMv8.2-A 64-bit instruction set, and the model is functionally accurate. The VCPU was compared to AXI VIP connection, which is a bus functional model of the CPU, to find out differences between traditional verification and co-verification flow. The measurements indicate that co-simulation with VCPU has a very good performance compared to traditional verification methods.

Presenter(s)
Mika Mäenpää

Nokia Networks

10:25 AM - 10:50 AM

Methodological Approach to Fault Injection Campaign Measurements

Track: Automotive

Addressing Random HW faults in Automotive designs requires a Safety Architecture with Safety Mechanisms (SMs) to monitor and detect their occurrence. Random Faults analysis is done through FMEDA (Failure Mode Effect Diagnostic Analysis), for computing the ISO 26262 metric. Validation of the FMEDA metric is done through Fault Injection testing. Fault Injection campaigns on today’s complex designs pose, however, a considerable challenge in terms of effort, computing resources and tool capacity. This presentation will discuss a methodological approach to Fault injection flow, which enables a faster convergence, from the perspective of large SoCs and complex IPs, of computing type. Various considerations, based on the design at hand, the type of Safety Mechanism and the available stimulus, will be discussed.

Presenter(s)
Jason Campbell

NVIDIA

10:25 AM - 10:50 AM

Containerization for EDA Workloads

Track: Cloud

We have been investing in technologies to accelerate our product enablement on the public cloud. These include job distribution, scalability, elasticity, data transfer, containerization, and more. We explored containerization as this technology provides many benefits such as isolation from host dependencies, bundling all application dependencies into single package, and lowering the overhead compared to virtual machines. In this talk, we will present our journey in enabling the framework for container support for our products both on-prem and on the cloud with the leading container HPC and native solutions, namely Singularity and Docker.

Presenter(s)
Jagdish Reddy

Engineering Director, Synopsys

10:25 AM - 10:50 AM

Faster Analog Design Closure with Early Parasitic Analysis Flow in Synopsys Custom Design Platform

Track: Custom-AMS

Catching potential electrical issues early can avoid extra design iterations. Synopsys custom design platform provides a unified workflow to accurately estimate, measure, extract and simulate parasitics by bringing signoff tools into the design process, enabling faster design convergence.

Presenter(s)
Denis Goinard

Synopsys

10:25 AM - 10:50 AM

*Network Switch Pre-Silicon Debug using ZeBu Record and Replay

Track: Emulation

The ZeBu platform provides a robust environment to meet the high validation requirements from a stimulus perspective but also enables efficient and deterministic debug via the ZeBu Record and Replay emulation technology. The Record and Replay technology significantly improves the time to waveform on long debug scenarios and provides a deterministic way to debug the complex test scenarios. It also significantly improves the time to waveform on long debug scenarios by allowing iterations from an intermediate snapshot close to failure point.

Presenter(s)
Sandhya Sastry

Broadcom

Presenter(s)
Utkarsh Prabha

Broadcom

10:25 AM - 10:50 AM

A Seamless Transition to PCIe 6.0 Designs with Optimized IP

Track: IP

In this session we will outline some of the considerations that designers must be aware of when they are ready to shift their designs to PCIe 6.0: such as doubling of the data rate, accessing a complete IP solution that offers optimized performance and seamless interoperability between the controller and PHY, achieving timing closure at 1+ GHz, and understanding the impact of the new PCIe 6.0 features including FLITs, new low power state, and PAM-4 signaling.

Presenter(s)
Gary Ruggles

Sr. Product Marketing Manager, Synopsys

10:25 AM - 10:50 AM

Enabling your Designers with IC Validator Launch

Track: Physical Verification

IC Validator Launch connects IC Validator with the user and the design environment by providing unified and customizable interface. Users today use command line interface to run and interact with IC Validator. IC Validator Launch provides an intuitive and easy-to-use graphical interface to launch IC Validator jobs. In this tutorial, learn how to setup a IC Validator run by specifying location of input data, options for the run, runset options customization, debug results with IC Validator VUE and integration with design tools such as IC Validator Workbench and Virtuoso.

Presenter(s)
Terry Meeks

Business Development Director, Synopsys

10:25 AM - 10:50 AM

*Design Variation Analysis and Variation Robustness Using PrimeShield

Track: Signoff I

This presentation demonstrates how we have used the new advanced capabilities introduced by PrimeShield in order to assure the design's target are met, and how we addressed non-linear variation issues at ultra low-vt designs.

Presenter(s)
Amir Grinshpon

Design Application Engineer, Intel

10:25 AM - 10:50 AM

*QuickCap Parasitic Extraction for Arm Physical Design

Track: Signoff II

This presentation will give an overview of our experience with Quickcap for Parasitic Extraction. We will review the extraction performance compared to our standard flow for production, extraction accuracy, usability and readiness with respect to Arm Physical Design IP production.

Presenter(s)
Tom Mahatdejkul

Arm

10:25 AM - 10:50 AM

*RTL Design Validation Using Static Connectivity Checks

Track: Silicon Test and Analytics

This presentation will review the methodology for validating our most recent Vision Processing Unit (VPU) RTL design, using static connectivity checks. The design of this project was very modular, with multiple configurations. The VPU design instantiates several thousand design units, each connected to the main DFT unit, or the functional logic, with SystemVerilog interfaces. This design style worked very well from an implementation perspective but often led to confusing and difficult to verify RTL structures. To accommodate the fast pace of changes, a high level of automation was required. As Lint checks and design-for-test verification goals are a part of our current flow, it made it straightforward to enable additional static connectivity verification. By gathering and post-processing design attributes, SGDC content was generated. Our Design Automation team was able to include the connectivity verification tests into our organizations source control Continuous Integration pipeline so tests were run on every RTL code commit and at regular intervals.

Presenter(s)
Allyn Hunt

Senior Design Engineer, Intel

Presenter(s)
Shravan Kumar Hossur Gopala Rao

Intel

Presenter(s)
Balajiraja Ravinarayanan

Intel

10:25 AM - 10:50 AM

*Lint Abstract Flow – A Hierarchical Approach to Enhance RTL-checking Quality with Faster Turn-around

Track: Static Verification

In the pursuit of zero Si bug in with predictable schedules, it is extremely important for RTL designers to signoff a good quality RTL to the verification and implementation team, to ensure that there are minimal ECOs. In the hierarchical SoC design where IPs are sources from both internal and external channels, it is challenging to signoff the RTL design issues because of the lack of abstract methodology for RTL-Lint. Therefore, it becomes mandatory to develop a comprehensive methodology for hierarchical SoC design which can address issues related to IP-SoC handoff by generating the lint abstract model and by integrating at the SS or SoC level. This presentation discusses abstraction methodology in the hierarchal SoC design which addresses issues related to IP-SoC hand-off by generating the lint abstract model at the subsystem level, and validating the abstract model at the SoC level. We will discuss various advantages and challenges related to abstraction flow RTL-Lint in the hierarchical SoC design.

Presenter(s)
Rohit Sinha

Intel

10:25 AM - 10:50 AM

*Refine the Tests Portfolio using VCS Coverage and Test Grading

Track: VCS/Verdi/VIP

This paper presents a detailed methodology to refine two important test portfolios widely used in the industry, “smoke” or “quick” regression and the larger coverage sign-off regression. The methodology for coverage sign-off regression aims to maximize coverage in minimum time through use of optimal test suite. The methodology for “quick” regression aims to maximize coverage of design with a limited number of tests and run time. This paper gives step-by-step guidance on how to achieve the goal based on VCS Coverage and Test Grading tools. The methodology has been applied within AMD’s Memory Controller group to achieve optimization of both test suites. As an additional benefit, it provides an opportunity to enhance coverage quality along the way.

Presenter(s)
Lingkai Shi

Advanced Micro Devices

10:25 AM - 10:50 AM

*System-Level Power Modelling for Processor Cores in Virtualizer

Track: Virtual Prototyping

At Bosch Automotive Electronics, mixed-signal sensor ASICs are an integral part of the solutions that we provide to the automotive industry. Such solutions require high energy optimizations while maintaining high performance and without compromising safety. In order to achieve this, Virtual Prototyping (VP) is used extensively to accelerate the software development for these ASICs and enable for an early design parameters exploration. In this work, we present how we used a novel power modelling technique to allow for an early power consumption estimate for the processor cores used in our designs. This work is solely based on the VP of such ASICs and is integrated into the Virtualizer suite. The approach achieves accurate power estimates on both white-box and black-box processor models.

Presenter(s)
Ahmed El-Yamany

 Robert Bosch GmbH, Automotive Electronics

11:00 AM - 11:25 AM

Getting Started with DSO.ai: A Tutorial

Track: Artificial Intelligence

DSO.ai is redefining the digital design process to deliver AI-grade engineering productivity. In this technical tutorial, we will introduce the DSO.ai design system, and discuss approaches to integration in production environments. We will take a detailed look at the broad range of design apps in DSO.ai and explain how app-driven development boosts productivity throughout the digital implementation cycle. We will conclude with experiences from applying the DSO.ai design system in production through actual deployment case studies.

Presenter(s)
Joe Walston

R&D Director, AI/ML Center of Excellence, Synopsys

11:00 AM - 11:50 AM

Replay: Facilitating Distributed Development of Safety Critical Automotive IP and SoC

Track: Automotive

Standards such as ISO 26262 define strict requirements, processes, and methods that all stakeholders IP vendors, sub-system and SoC developers must abide by when designing safety critical automotive products. One such requirement is the Development Interface Agreement (DIA) which defines the interactions, interfaces, responsibilities, dependencies and work products to be exchanged between customers, like Infineon, and suppliers for all distributed safety related activities. In this session, we will explain the details of distributed development based on DIA and outline the different activities for which DIAs must be signed during a distributed development process. In the second part of the presentation, Infineon will highlight their approach on meeting SoC-level functional safety objectives while closely collaborating with Synopsys.

Presenter(s)
Vladimir Litovtchenko

Functional Safety Director, Synopsys

Presenter(s)
Dietmar Koenig

Infineon

11:00 AM - 11:25 AM

Design Processing and Verification Using Kubernetes Based Hybrid Cloud Infrastructure

Track: Cloud

IBM and Synopsys have been working together to investigate the advantages and trade-offs of migrating high performance EDA applications to the cloud. In this work, we describe the incorporation of synopsys icv validator tools into a digital design flow enabled on a hybrid cloud infrastructure. Large chips require significant compute resource for design and validation of data. Our emphasis in this work is to reduce the process time by running synopsis icv validator applications in kubernetes based containers. Virtual machines are configured with defined cpu and memory requirements. Runtime improvements are realized by taking advantage of icv distributed and multi-threaded capabilities. The advantage of kubernetes is that they can be ported to any cloud environment. We discuss the advantages and disadvantages of running applications using on premis and hybrid cloud models.

Presenter(s)
Clifford Osborn

Senior Engineer, IBM

11:00 AM - 11:25 AM

Improved QoR and Productivity for Analog Layout with Custom Compiler’s Visually-Assisted Layout Automation

Track: Custom-AMS

Engineers can reduce analog layout TAT by using Custom Compiler's visually-assisted layout automation technology. It provides productive and easy-to-use features for analog placement, routing and template-based design reuse methodology to achieve high quality layout.

Presenter(s)
Karun Sharma

Synopsys

11:00 AM - 11:25 AM

*Fast RTL Prototyping and PPA Exploration Using RTL Architect

Track: Digital Design

In this presentation, we describe the use of RTL Architect for RTL physical prototyping and tuning. RTL Architect provides a cockpit for the designer to isolate physical impact on performance, congestion and power. We will further discuss how the RTL Architect feature of parallel space exploration and FAST synthesis can be used to explore the impact of implementation parameters - Vt mix, floorplan shape, macro placement, etc. We will conclude with design flow and results.

Presenter(s)
Girish Prabhu

Google

Presenter(s)
Ankit Agrawal

Google

11:00 AM - 11:25 AM

800G Ethernet SoC Validation

Track: Emulation

Ethernet switch designs continue to grow in port count and part speeds. We will show how virtual network testing can drive the DUT with a broad range of packet scenarios to enable stress testing of new architecture.

Presenter(s)
Rashid Kukkady

Synopsys

11:00 AM - 11:25 AM

Deciphering the MIPI Standards for Camera and Display

Track: IP

In this session, we will explain the benefits of MIPIs CSI-2, DSI/DSI-2 D-PHY, and C-PHY standards for camera and display applications by highlighting some of the key features such as D-PHYs 4.5 Gbps bandwidth, C-PHYs 3.5 Gsps bandwidth with a 3-wire architecture, CSI-2s maximum throughput for mega-pixel cameras, and DSI/DSI-2s high resolution and bits per pixel. In addition, we will highlight the advantages of integrating MIPI C-PHY and D-PHY for higher performance in todays visual applications.

Presenter(s)
Licinio Sousa

Sr. Product Marketing Manager, Synopsys

11:00 AM - 11:25 AM

*Enable Level Shifter Insertion with Multiple Power and Bias Domains

Track: Low Power Design

In the area of ultra-low-power applications, such as for IoT, effective implementation of multiple power domains is imperative. Utilizing Enable Level Shifter Cells (ELS) the right way, to allow interaction between the domains, might not necessarily become an “out of the box” easy task. In particular, when used in technologies, where back gate biasing is utilized in addition. This paper concentrates on how ELS cells can be efficiently implemented to serve the need of specific scenarios. A key focus hereby is the usage of IEEE-1801-2013 (UPF 2.1) with Design Compiler (DC-NXT).

Presenter(s)
Farid Labib

GLOBALFOUNDRIES

11:00 AM - 11:25 AM

Accelerating Physical Signoff Convergence for 5nm and 7nm Designs

Track: Physical Verification

Learn about IC Validator technology advances to enhance full chip physical verification productivity and customers’ experiences with IC Validator on cutting-edge 7nm and 5nm design tape-outs. We will share challenges with full chip verification of advanced node designs and their methodology with IC Validator for faster physical verification closure. Plus discuss scaling IC Validator jobs to hundreds of cores to achieve full chip signoff within hours for 5nm designs.

Presenter(s)
David Enright

Principal Design Engineer, Acacia

Presenter(s)
Jae Hoon Kim

Samsung Electronics

11:00 AM - 11:25 AM

*Parametric Timing Success-Rate Improvement using PrimeShield

Track: Signoff I

As device dimensions continue to shrink, process variability has become an important factor in the performance of a design. It is becoming increasingly clear that a significant difference between simulated performance, as measured in timing sign-off, and Silicon performance is due to this process variability. The traditional approach to manage process variability is the use of design margins - these methods have been refined, aided by improvements in variation modelling for signoff with LVF. These refinements provide better control than simple margins and help to improve design quality for variance. However, these approaches still have a high cost in power and area, when targeting the entire material range for parametric robustness, particularly for smaller geometries like 5nm/3nm. In this paper, we will discuss how we used PrimeShield to improve the projected parametric timing robustness in our design and highlight the challenges. We will conclude with proposed approaches to validate the parametric robustness improvements and further work.

Presenter(s)
Gautham Narayanarao

Google

11:00 AM - 11:25 AM

*Buried Signal Line Exploration for sub-5nm SRAM Design

Track: Signoff II

Buried power rail (BPR), i.e., metal wires below the active transistors, has been proposed for routing power and ground lines to improve the performance and density of standard cells and mitigate the increasing RC parasitics at sub-5nm CMOS technology nodes. We will present the Buried Bit-Line (BBL) SRAM technique which utilizes buried metal interconnects for signal routing instead of power or ground routing to achieve better SRAM performance and lower power consumption while requiring minimal process flow changes to the buried power rail technology. We will show how design technology co-optimization (DTCO) is performed using Synopsys Quickcap for high-accuracy parasitic extraction of buried metal rail to identify optimal BBL parameters.

Presenter(s)
Rahul Mathur

Staff Design Engineer, Arm

11:00 AM - 11:25 AM

RTL Based DFT Partition Scan Architecture

Track: Silicon Test and Analytics

As design complexity increases with multiple voltages and power domains, it brings challenges in the design and implementation of physical design-friendly design-for-test (DFT) architecture. While some of the complex designs with flattened physical implementation give the best QoR, it makes traditional top-down DFT flow more challenging with multiple voltages and power domains. RTL based DFT partition scan architecture helps to achieve the best QoR with a flattened physical implementation strategy. In this approach, various DFT components get added to DFT partitions at the RTL stage which helps to achieve faster turnaround time and best QoR in the physical implementation. DFT partitions and the corresponding DFT components are decided based on various metrics like voltage domains, power domains, flip-flop count, clocking, IP interfaces, physical partitions, feed-throughs, ports location, placement blockages, etc. DFT components include multiple codecs, on-chip clock controllers, scan pipelines, scan decode logic, scan wrapper cells and shift power control logic, etc. This paper illustrates the RTL based DFT partition scan architecture and results.

Presenter(s)
Vevekanenda Gonugunta

Google

Presenter(s)
Rajesh Gottumukkala

Google

11:00 AM - 11:25 AM

Noise Reduction in VC Spyglass Platform with Machine Learning and Formal Technology

Track: Static Verification

In this tutorial, we will demonstrate how VC SpyGlass is helping to reduce noise with Machine Learning technology for CDC verification and Formal analysis for Lint verification. Users can see 20-30x productivity gain in their CDC verification cycle and 30-35% additional noise reduction with Formal Enabled Lint.

Presenter(s)
Shylaja Sen

Synopsys

11:00 AM - 11:25 AM

*Automatic Functional Coverage Generation

Track: VCS/Verdi/VIP

Technology advances allows for the creation of larger designs whose verification is assured by functional coverage which checks all aspects of the design are tested. Basically, coverage model can be segregated as what to do and how to do. Consequently, real challenge lies on how part i.e. how to write cover properties error-free, concise yet robust with accurate options which language provides. This presentation covers how to overcome mentioned complexities through an automation done by maintaining a coverage matrix (in form of .csv/.xls) which consists of all functional requirements to be covered and that will be converted into System Verilog functional coverage code through automatic coverage generation script. This approach minimizes verification engineer’s time and effort by 70% and breaks language barrier.

Presenter(s)
Priyanka Singh

eInfoChips

11:00 AM - 11:25 AM

Hybrid Emulation – Accelerate Software Enablement in Automotive SoC

Track: Virtual Prototyping

There is an increased demand for software bring-up with emulation for multi-core Automotive SoCs. Success of Day-1 software bring-up lies in the quality of software run on pre-silicon platforms, prior to the tape-out. Software functionalities critical for Day-1 bring-up range from qualifying the reset sequence, clock configuration, boot sources, DRAM initialization, to running a full OS boot such as Linux. Virtualizer Development Kit (VDK), Zebu Emulation and the integration of the two (Hybrid Emulation) helps emulate multi-core SoC designs to qualify these critical software functionalities well before tape-out providing a shift-left methodology. This shift-left approach helps reduce the risk and cost of critical post-silicon bugs resulting in mask re-spins and provides a way to deliver engineering samples to customers earlier in the development cycle. In Hybrid Emulation, various optimizations were implemented to speed up software execution and accelerate Software bring up faster than pure emulation. For instance, in Hybrid Emulation the application core clusters are off loaded to run in Virtual Prototype to provide better performance. This presentation describes our use model of U-boot and Linux bring-up on a Hybrid Emulation platform along with the challenges and benefits observed. It also captures debug techniques used to troubleshoot issues using standard Zebu/VDK features [SW Analysis, Triggers, Waveforms etc.] and JTAG debugger. Lastly, results from all platforms including Zebu emulation, Hybrid Emulation and VDK simulations are published from our findings.

Presenter(s)
Bharadwaj Ramanujam

NXP

Presenter(s)
Jonathan McCallum

Synopsys

Presenter(s)
Mojin Kottarathil

Synopsys

11:25 AM - 11:50 AM

Towards Auto-Convergence in Digital Design: Using DSO.ai to Maximize PPA Benefits

Track: Artificial Intelligence

For todays high-performance ASICs, designing on leading process node with short execution schedules while achieving best possible PPA is essential for developing competitive products. Achieving predictable convergence for RTL2GDS design using APR tools is heavily dependent on design input collaterals quality and is generally susceptible to changes in RTL, floorplan, stdcell/EBB libraries, design constraints etc. Exploring APR convergence recipe changes for each change in design/process collaterals to continue maximizing the PPA becomes a challenge as isolating effects of each change and tuning APR optimization for PPA is non-trivial. This problem gets harder for designing multi-million instance SOC/IPs being developed on leading process nodes and includes new SOC/IP architectures where changes in RTL, floorplan are large and constant. This presentation focusses on novel DSO.ai solution which uses ML/AI techniques to simplify design optimization search space exploration. DSO.ai works in conjunction with APR implementation tools like Fusion Compiler and provides all necessary capabilities to permute various tool options, design constraints, design specific optimization strategy/recipe variations and learn from each APR run to predict and optimize the settings for achieving target PPA goals. The learning process is continuous over multiple runs as well as iterations which helps in studying the effect of each parameter and keep optimizing the settings for improving PPA as well as drive towards out of the box convergence. We present a case study focusing on PPA improvement for representative designs from a graphics-IP implementation in SOC. Using DSO.ai, we were able to reduce total power of these representative designs by upto 10% without affecting other metrics negatively. We also discuss potential use models for DSO.ai in APR implementation cycle to achieve auto-convergence and conclude with recommendations to maximize the PPA benefit with DSO.ai.

Presenter(s)
Milind R Mahajan

Intel

11:25 AM - 11:50 AM

*Google Chip Design Team’s Cloud Journey: The Google on Google Story

Track: Cloud

Google is often associated with one of the many billion-plus user services such as Search and YouTube, but we have also been building chips for the past few years. A particularly notable effort is the Tensor Processing Unit family of chips. We describe in this presentation the path we took to transition our design and verification teams to leverage cloud.

We looked at cloud to meet three primary goals: Elasticity, State-of-the-art Compute and Data-driven Insights.

Cloud offered us several advantages, and we have benefited from our migration. Using cloud improved provisioning time drastically, removed uncertainty, improved reliability and enhanced designer productivity. In our presentation, we will share our learnings, provide details about the challenges we faced, and discuss potential architectures that could be leveraged by external design teams. In particular, we will discuss verification and design workload migration and benefits.

Presenter(s)
Ishai Ben-Dov

Google

Presenter(s)
Kent Dozier

Google

Presenter(s)
Steven Chan

Google

11:25 AM - 11:50 AM

Template Based Analog Layout Flow at SK Hynix

Track: Custom-AMS

SK Hynix established circuit/arrangement standardization for frequently used Amplifiers (Legacy Design) and developed automation flow by actively utilizing Synopsys's Template Manager function. During the development period, we were able to reduce the complexity of template production and increase the completeness through the improvement of the Synopsys Template Manager (Dummy, Resistor, etc.) and the development of the Flexible Hierarchy Template function. By making templates and applying flows to about 30 amplifiers, we were able to reduce the design time required for the design by more than 2x times compared to the previous one. In addition, it is expected that the flow can be expanded according to the level of classification of Legacy Design in the future.

Presenter(s)
Jinman Kang

SK Hynix

11:25 AM - 11:50 AM

Achieving Best Quality RTL for Faster Design Closure with Features-Added Physical Aware Synthesis (FPAS)

Track: Digital Design

With increasing complexities in design and continuously evolving process, it is a challenging task to maintain a tight schedule and be ahead of competition to gain leadership. While architects and Register Transfer Level (RTL) design teams explored ideas to partition the design and produce quality RTL, Physical Design (PD) backend team worked on many new aspects to achieve the most optimal Quality of Results (QoR). While we have improved the collation between FE/BE over the past years, but it still has room for further improvement. Frontend handoffs needs to be more predictable to backend (PD team) and would help to reduce Synthesis/Place & Route iterations and faster overall convergence. Features-Added Physical Aware Synthesis (FPAS) provides us with multiple benefits, ranging from improved timing QoR by identify critical paths, early reliable congestion analysis, and power estimation which aligns closely to Fusion Compiler. It also provides additional benefits w.r.t partitioning the design along with pipelines that can be added to meeting timing as opposed to waiting for physical design feedback and hence saving iteration time. In addition, FPAS allowed cross-probing from RTL to timing paths and layout in single user interface, which allow ease-of-analysis for designers. Our initial studies reported at least 2x runtime improvement compared to default synthesis tool. For timing, FPAS showed approximately 90% timing paths are correlated within 10% margin. Modules placement, density and congestion map are well correlated. Less than 15% power different observed compared to default synthesis tool.

Presenter(s)
Cheen Kok Lee

Intel

11:25 AM - 11:50 AM

Staying Ahead in 5G System Verification

Track: Emulation

While we all experience the first 5G services, the development of 5G silicon remains a race that will be on for many years to come. System verification of the evolving 5G standard requires fast execution engines and fully 5G compliant test vectors. We will demonstrate an industry leading solution based on ZeBu.

Presenter(s)
Susheel Tadikonda

Synopsys

11:25 AM - 11:50 AM

An Insight into the Evolution of HBM3

Track: IP

HBM DRAMs, mainly for GPUs and accelerators, provide high throughput per channel at a low power per bit transferred. For applications seeking higher memory density and bandwidth than HBM2E, the industry is now anticipating the release of next-generation HBM3 which is expected to provide higher transfer rates with even better performance. In this session, we will focus on the introduction of HBM3 which is expected to double the density to 64GB/s with 512 GB/s of bus size, all essential requirements for high-performance computing.

Presenter(s)
Brett Murdock

Sr. Product Marketing Manager, Synopsys

11:25 AM - 11:50 AM

*How to Achieve the Best PPA on an Ultra-Low Power STM32 Microcontroller; SAIF Driven Synthesis Flow

Track: Low Power Design

“Ultra-low power” and “high performance” are keywords nowadays. Designs are facing increasing complexity: timing critical with power consumption reduction and minimum area targets, multi-voltage designs and multi-supply hard-macros. This presentation will highlight a methodology to achieve the best performance, power and runtime results with an RTL SAIF-driven synthesis flow on an ultra-low power Arm microcontroller-based design with multiple switchable power domains embedding retention registers.

Presenter(s)
Nathalie Meloux

CAD & Design Support Engineer, STMicroelectronics

11:25 AM - 11:50 AM

Advanced Reliability Checking with IC Validator PERC

Track: Physical Verification

IC Validator PERC is a reliability verification solution that enables customized checking for EOS/ESD/ERC rules. IC Validator PERC provides fast performance, scalability and intuitive debugging for reliability verification. In this tutorial, learn about latest advances in IC Validator PERC and new capabilities including: Current density checking with StarRC extraction, Point-to-point resistance checking with StarRC extraction, Voltage based spacing checks, topology and layout checks.

Presenter(s)
Frank Feng

IC Validator Technologist, Synopsys

11:25 AM - 11:50 AM

PrimeShield Design Robustness Analysis and ECO

Track: Signoff I

Increasing variations at advanced nodes pose serious challenges to robust product functionality and performance. To address these, design teams add guardband margins and signoff at higher sigma to manage risk, resulting in over-designing, thus paying higher PPA cost. PrimeShields innovative ML-driven statistical engine enables full statistical design variation analysis, lowers the overall pessimism, and in some cases catches potential risks of design optimism. In this presentation, we will discuss how PrimeShield rapidly identifies and drives optimization of bottlenecks at, cell, path, and design level. We will also cover how the new robustness ECO methodology can be effectively used.

Presenter(s)
Sahil Bargal

Synopsys

11:25 AM - 11:50 AM

Extraction Innovations for Advanced Node Digital Design

Track: Signoff II

StarRC continues to invest and innovate in scalable runtime and capacity of core extraction and field solver technologies. Improving QOR, TAT & designer productivity while providing golden signoff extraction are the key aspects driving product roadmap. This session will provide an overview of our current technologies, innovation in adv. Nanosheets/GAA processes, new features for digital design flow & integration with digital platforms.

Presenter(s)
Krishnakumar Sundaresan

Synopsys

11:25 AM - 11:50 AM

Demonstration of TestMAX SMS Memory Test & Repair Flow

Track: Silicon Test and Analytics

The TestMAX Manager platform is the latest solution from Synopsys which enables the shift-left of the complete DFT insertion flow using RTL. This presentation demonstrates the flow adopted by Samsung to implement the TestMAX SMS flow for memory test & repair. Power (UPF) and placement (DEF) based implementation is successfully used to insert the SMS components in a back-end friendly way. Integration at the SoC level is done using the IEEE 1500 SMS component configured by a TAP Controller.

Presenter(s)
Brandon Kim

Samsung Electronics

11:25 AM - 11:50 AM

A Comprehensive UPF Coverage Methodology to Avoid Late Si Issues

Track: Static Verification

The increasing presence of power management with high numbers of switchable power domains at earlier stages in the design cycle, and its effect on functionality, requires simulations at RTL stage to be power-aware to ensure correct power management. Because of the complexities related to voltage domain crossings, achieving high UPF coverage has been an issue in Client and IOTG programs. However, attaining a high low power coverage for the verification signoff is necessary to ensure that all aspects of power-aware simulations are covered with the test scenarios, and there are no late Si findings. This presentation discusses the comprehensive methodology to achieve high (90% and above) UPF coverage in the IOTG SoC Design. In addition, we will discuss various low power challenges pertaining to poor UPF coverage.

Presenter(s)
Rohit Sinha

Intel

11:25 AM - 11:50 AM

*Optimizing Test Execution Time for Coverage

Track: VCS/Verdi/VIP

Regression testing plays a key role in determining the quality of an IP. These regression tests can take a long time to execute. This in turn results in long turnaround times when issues are found and need to be debugged and fixed. In addition, there is the issue of using a lot of computing resource and time. We will present an algorithm, to decrease regression time while still achieving desired coverage metrics.

Presenter(s)
Ramesh Kizhappali

Intel

11:25 AM - 11:50 AM

Early Software Development on a First Generation AI Chip with Virtualizer

Track: Virtual Prototyping

As a startup, one typically doesnt have access to a reference platform or to previous versions of a chip that can be used as a starting point for software development. There are multiple paths one can take to develop the software, but at the end of the day, the entire team needs to have some reference of the hardware being designed, a software development platform, as well as a reference to test new IP's and interconnections. One of the reasons SiMa is generating so much buzz is not just the fact that we have an interesting hardware proposition, but also our software is a big differentiator. We pride ourselves in making the transition from PC based AI application development to the firmware application very easy. Virtualizer and VDKs have helped us not just in aggregating our custom IP together, but also in testing the clock cycles, dependency delays and much more. In this presentation we will cover how we have used Virtualizer/VDK for the following tasks: Verify the boot up sequence of the heterogenous system with 12 cores, Facilitate SW development for custom IP model integrated into the SoC and Validate complex SW architecture flow build-out.

Presenter(s)
Naveen Sangeneni

SiMa.ai

12:00 PM - 12:25 PM

Synopsys Testcase Packager: Seamless Migration and Execution for EDA Workloads on Cloud

Track: Cloud

Synopsys Testcase Packager (STP) is the next generation, application-agnostic, zero-integration testcase packaging technology for all Synopsys Products. EDA environments are highly complex with different dependencies and undergo a high frequency of unregulated changes. STP has significantly improved the productivity by automatically capturing a complete customer testcase and reproducing it in a remote environment. Typically, EDA workloads have large data sizes which makes uploading to Cloud impractical during peak usage e.g. 10,000+ cores. STP solves this with "EDA Data Environment" synchronization. That is, pre-populate and continually auto-synchronize data between on-premises and Cloud for on-demand execution.

Presenter(s)
Jishnu Dave

Senior Software Engineer, Synopsys

12:00 PM - 12:25 PM

AI-Driven Design Space Optimization Case Study

Track: Artificial Intelligence

In SOC design flow, physical design is a black box problem and it is very difficult to understand where the output comes from. Artificial intelligence offers good solutions to explore the design solution space and get better PPA. In this session we will share details of our work with DSO.ai at Samsung Foundry and examine the observed improvements and benefits of the AI-driven approach.

Presenter(s)
Chang Ho Han

Samsung Electronics

12:00 PM - 12:25 PM

Replay: Ensuring Functional Safety of Memory IP Using TestMAX CustomFault

Track: Automotive

Memory real estate is continuously increasing, reaching more than 80% on present day SoCs. In Automotive SoCs, Memory IPs are used for various applications ranging from ADAS to navigation and infotainment. SoCs designed for life critical applications like ADAS (ASIL-D category in ISO26262 standard) go through rigorous functional safety checks and FMEDA (Failure Modes, Effects and Defect Analysis) becomes a necessary step to systematically predict the failure rate of all IPs used in such subsystems. Among various objectives of FMEDA, in this paper, we focus on the requirement for fault analysis and discuss how we are able to use TestMAX CustomFault to perform fault analysis to ensure functional safety of our embedded Memory IPs catering to the Automotive market.

Presenter(s)
Kedar Janardan Dhori

STMicroelectronics

12:00 PM - 12:25 PM

Standard Cell Design Productivity Improvement with Layout Editor Assisted Layout Automation

Track: Custom-AMS

We will present a novel flow for standard cell design that uses advanced features in Layout Editor to reduce layout time. Our flow includes deployment of schematic driven layout (SDL). SDL is a powerful technique for improving layout productivity, but not many standard cell designers are open to using it. We had developed a methodology leveraging advanced features in Layout Editor that made adoption of SDL much more practical. This included capabilities for hierarchy manipulation, automatic and interactive device chaining, interactive analysis, etc.

Presenter(s)
Anjali S

Intel

12:00 PM - 12:25 PM

Case Study: Optimize and Configure Synopsys DesignWare IP with RTL Architect

Track: Digital Design

This session will provide a case study of how the Synopsys R&D team for DesignWare ARC EV Processor IP used RTL Architect to accelerate their IP’s time-to-market. It will explain how the R&D team used predictive data from RTL Architect to make smart decisions quickly, resulting in a faster path to an optimized IP configuration.

Presenter(s)
Fergus Casey

Synopsys

12:00 AM - 12:25 AM

*Low Power Emulation of Automotive SoC

Track: Emulation

There is an increased demand for low power Automotive SoCs. Minimizing leakage power using UPF is one of the techniques used to reduce power consumption of complex SoCs. Consequently, pre-silicon emulation needs to verify the low power behavior of hardware and software drivers. This presentation describes our use model of UPF based emulation along with the challenges and benefits observed. In verification the powered down domain is simulated using Xs, whereas Zebu implements it with pseudo-random values and register scrambling via run-time power management APIs. We also describe the various techniques used for low power debug such as Verdi power aware debug for simulation and FWC/iCSA debug features on Zebu. This shift-left of low power verification and validating u-boot/linux OS with power management drivers on Zebu enables us to catch power related bugs earlier and thus reduces the risk and cost of silicon re-spin.

Presenter(s)
Rashmi Finavia

NXP

Presenter(s)
Aditya Musunuri

NXP

12:00 PM - 12:25 PM

Key Applications for In-Chip Sensing & PVT Monitoring

Track: IP

The latest SoCs on advanced semiconductor nodes especially FinFET, typically include a fabric of sensors spread across the die and for good reason. But what are the benefits? This presentation explores some of the key applications for in-chip sensing and PVT monitoring and why embedding this type of IP is an essential step to maximise performance and reliability and minimise power, or a combination of these objectives. The presentation will also examine use cases from key application platforms including AI, Data Center, Automotive, 5G and Consumer.

Presenter(s)
Stephen Crosher

Synopsys

12:00 PM - 12:25 PM

*Innovative Solutions for Complex Hierarchical UPF Design Implementations

Track: Low Power Design

UPF has already become part of the SoC implementation flows worldwide and is the de-facto standard for low power implementation. As designs in Intel are getting more and more complex and assorted from different IP groups, the concept of a flat UPF which encompasses all power information in one merged file is becoming inefficient, resource consuming and error prone. This presentation will discuss the need for a Hierarchical UPF approach which iintegrates multiple UPF files from different sources into the design seamlessly and the new challenges is raises for backend implementation tools.

Presenter(s)
Adi Yacobson

Intel

12:00 PM - 12:25 PM

*Synopsys ICV Live Enablement in IBM Advanced Node Processor Design Environment

Track: Physical Verification

In the VLSI physical design phase, the ability to verify the working set of layout geometries quickly and accurately is critical to meeting processor roadmap targets. This is especially valuable in modern, advanced technology nodes where design rule complexity is increasing at an exponential rate. This paper shows how the enablement of Synopsys ICV Live in the IBM processor design environment significantly reduced PD cycle turn-around-time for library cell and array designers. Additionally, the ability to integrate ICV Live into the existing layout editor while using the sign-off runset inherently improved overall designer efficiency.

Presenter(s)
Josh Martin

IBM

12:00 PM - 12:25 PM

*Utilizing TestMAX SMS Algorithm Programmability to Reduce Unnecessary Timing Signoff Effort on Dual Port Memories

Track: Silicon Test and Analytics

System-on-chip (SoC) designs are growing increasingly complex at advanced nodes and the time-to-market windows are shrinking rapidly. In the face of these challenges, timing signoff of digital designs has become increasingly critical, time-consuming, and the last step toward design closure. Hence, reducing timing signoff effort is becoming an important topic for all chip development engineers. These slides look at how to leverage SMS algorithm programmability to reduce unnecessary effort on Dual Port memories and speed up the timing signoff process.

Presenter(s)
Peng Minqiang

Sanechips

12:00 PM - 12:25 PM

*Optimizing PCIe System-Level Performance in a Pre-Silicon Environment

Track: VCS/Verdi/VIP

PCIe subsystem performance has a direct impact on system performance for many use cases (for e.g. 800G/1.6T Ethernet). Given the importance of PCIe interface performance, waiting until post-silicon before doing PCIe performance verification can result in re-spins or longer time to market. Therefore, it is important that there is a robust methodology to verify PCIe interface performance in pre-silicon. We will discuss a pre-silicon PCIe performance verification infrastructure (including the required VIP features) and methodology that will help de-risk SoCs with PCIe interfaces. We will detail a set of bare-metal benchmarks based on Accelerator, NIC, and Storage use cases that can be run using our proposed verification infrastructure. We will also discuss a theoretical approach for estimating the achievable PCIe link bandwidth. Results for a selection of the bare-metal performance tests will also be discussed as an example of what the solution is capable of.

Presenter(s)
Robert Green

Arm

12:00 PM - 12:50 PM

Virtual Prototyping for Continuous Integration Testing of Embedded SW stacks

Track: Virtual Prototyping

Software methodologies such as Continuous Integration and Delivery and Test Driven Development have become ubiquitous in recent years. This has been a very necessary development and allows large teams to collaborate effectively in the development and testing of the complex software stacks we now find in embedded automotive and AI applications. We find these methods in use across the product development lifecycle from initial, pre-silicon development thru software integration with hardware, to deployment of software variants once a product has launched. A significant issue facing such set-ups is the cost of custom hardware to run the tests that ensure software quality is maintained throughout the product lifecycle. It this tutorial we will show you how Virtual Prototypes are integrated with application development and debug, image building, revision control, and Continuous Integration platforms to scale up and fully automate the software testing process. We will demonstrate the flow based on the Eclipse based Virtualizer Studio Integrated Development Environment, GIT version control, and the Jenkins automation server. This setup accelerates turn-around time and reduces costs over running these tests on expensive and hard to maintain hardware.

Presenter(s)
Sam Tennent

Synopsys

12:25 PM - 12:50 PM

*Machine Learning Based Root Cause and Power Aware Analysis in Asynchronous Design

Track: Artificial Intelligence

As design complexities are continuing to grow exponentially in the asynchronous designs, resulting in an increase in the CDC/RDC violations report volumes from 10K – 1M violations. Manual debug of these violations is not only a challenging task but is also time-consuming requiring expertise and domain knowledge. This presentation discusses applying machine learning algorithm to identify the root cause of the issues which could result in huge number of the effect violations. We will discuss how the goal of the technology is to reduce the debug turnaround time by creating smart cluster and identifying root cause to minimize debug time and effort.

Presenter(s)
Rohit Sinha

Intel

12:25 PM - 12:50 PM

Replay: Analog Fault Simulation for ISO 26262 Using TestMAX CustomFault

Track: Automotive

This presentation describes the application of the Synopsys analog fault simulator TestMAX CustomFault at TDK-Micronas. It gives an introduction to the tool, the methods used in it, and its application for the determination of some ISO26262 metrics.

Presenter(s)
Erich Gottlieb

Senior EDA Engineer, Micronas

12:25 PM - 12:50 PM

Accelerate Chip Integration While Improving SPEF Quality for Timing Closure with the Custom Compiler Solution

Track: Custom-AMS

Xilinx ® IC designers have benefitted from Custom Compiler technologies to increase design reliability and reduce late-phase editing iterations, thus improving productivity and design closure. Key features, such as the schematic-driven-layout (SDL) process, retains critical nets in the generated layout, alleviating the need to correct connectivity downstream. To maximize reliability, built-in restrictions prevented incorrect logic modifications. In addition, resistance and capacitance calculations, shield creation and reporting, and via checking on partially completed designs promoted efficient processes that resulted in reliable designs. By reducing costly post-layout modifications and iterations, the in-design assistants also contributed to further productivity gains while delivering reliable design closures predictably.

Presenter(s)
Denis Keane

Xilinx

12:25 PM - 12:50 PM

Formality ECO: Automated Functional ECOs with Hand-Crafted Quality and Minimal Effort

Track: Digital Design

This session will include a brief tutorial on recent advances in FM ECO. The session will also include a case study from Alphawave relaying their recent experience leveraging FM ECO to quickly implement similar ECOs to multiple versions of their IP quickly.

Presenter(s)
Satyanarayana Hammigi

Alphawave

Presenter(s)
Steve Lamb

Synopsys

12:25 PM - 12:50 PM

*PCIe RAS DES Framework for SoCs

Track: IP

Due to shrinking silicon process nodes, transistors are getting smaller and smaller making SoC subject to failures due to external disturbances (EMI, heat, power surges etc.). As a result, SoC designers who use PCIe as the main communication interface in their SoCs are looking for ways to bulletproof their design by implementing advance Reliability, Availability and Serviceability (RAS) mechanism. DesignWare controller includes a set of RAS DES features which can make debugging much simpler but unfortunately is unexplored. In this paper, some of the potential PCIe hazards faced by SoC designers and SoC application users are explained. This paper also showcases the implementation and usage of proposed PCIe RAS DES framework in the Linux subsystem. The proposed framework highlights the detection, recovery and prevention of those hazards without use of any expensive hardware based PCIe analyzers.

Presenter(s)
Pankaj Kumar Dubey

Staff Engineer, Samsung Electronics

12:25 PM - 12:50 PM

*Tower Support for Synopsys' Analog / RF / Photonics Design Flows​

Track: Physical Verification

This presentation will cover considerations for developing PDKS that deliver maximum productivity to designers of analog, RF and silicon photonics ICs. Tower fully supports the Synopsys Custom Design Platform through a robust set of iPDKs. These include support for advanced productivity features in Custom Compiler, HSPICE models for Synopsys SPICE and FastSPICE simulators, and runsets for IC Validator physical verification and StarRC extraction. We will also provide photonics elements for OptoCompiler for selected process nodes. Plus, the development flow and QA of iPDK, how we enrich it and reference design example for each of the supported process.

Presenter(s)
Ofer Tamir

Managing Director Design Enablement & Support, Tower Semiconductor

12:25 PM - 1:50 PM

Innovative Design-for-Test (DFT) Methodology for AI & Automotive SoCs

Track: Silicon Test and Analytics

In the emerging era of large-scale SoCs comprised of complex IPs, typically designed for AI and automotive applications, it is essential to embrace an innovative approach to overcome numerous DFT challenges. Therefore, a solution must be scalable, robust, and functional safety (FuSa)aware, in addition to meeting the fast time to market aspect. This presentation explains automotive SoC requirements and challenges, as well as an advanced shift-left design-for-test methodology and its criticality. This innovative approach, with the described solution, allows full de-coupling between functional and test design aspects of a safety-critical SoC.

Presenter(s)
Yehonatan Abotbol

Mobileye

12:25 PM - 12:50 PM

Automation Accelerates Verification Closure upto 10X for next-gen SoCs- Simple, Scalable, & Efficient

Track: VCS/Verdi/VIP

Data centers and cloud services are the heart of digital transformation. With the move to greater complexity, problems that were once isolated to individual design blocks are now system-level concerns. Cache coherency is just the latest of these concerns. Every SoC team is facing or will face this challenge of accelerating coverage closure to meet tape out schedules. Proper verification requires fast cycle-accurate models, coherency-aware system level scenarios & most important to ensure the coherency is maintained across the System by System Monitors.This tutorial presents a highly automated approach to cache coherency verification at the SoC level providing upto 10X overall efficiency : generation of test cases to stress every aspect of a multi-processor, multi-memory, multi-level cache design. This solution requires no specialized knowledge of cache algorithms or of the underlying generation technology.

Presenter(s)
Satyapriya Acharya

Synopsys

1:00 PM - 1:25 PM

*Unsupervised Machine Learning Based Root Cause Analysis of Front-End and Back-End Low Power Issues

Track: Artificial Intelligence

As the design complexities continue to grow exponentially, causing an increase in the violations from 10k–1M, debugging and fixing the low power issues are not only time-consuming but also requires domain expertise to analyze and fix the issues in a timely manner. As low power issues have to be validated across all the domains from RTL to Signoff, there is an absolute requirement of a low power debugging feature which could group all the issues in such a manner that designers only have to focus on the root cause of the issues rather than dealing with lakhs of violations. This presentation will discuss the RCA methodology and showcase the benefits witnessed at different phases of the designs. We will discuss how unsupervised machine learning based root cause analysis feature has been deployed successfully in our work and how debug turn-around-time has been reduced by enabling this feature in the frontend as well as in backend.

Presenter(s)
Santanu Kundu

SoC Design Engineer, Intel

1:00 PM - 1:25 PM

Samsung AMS Design Reference Flow for Advanced Node

Track: Custom-AMS

AMS design challenges have significantly increased with complex design requirements at advanced CMOS processes. Samsung's advanced node AMS Design Reference Flow is intended to reduce this design complexity and improve design productivity at advanced technology nodes. The flow demonstrates to the end users how Samsung foundry PDK’s are well in sync with the latest AMS design platforms. Samsung Foundry customers can now take advantage of the most advanced features for circuit design, performance, reliability verification, automated layout, block and chip integrations for custom and digitally-controlled analog-based design on Synopsys’ Custom Compiler, simulation environment, and simulators. In this session, we will talk about Samsung’s AMS Design Reference Flow from schematic to layout verification and the future.

Presenter(s)
Seongkyun (Gabriel) Shin

Samsung Electronics

1:00 PM - 1:50 PM

Memory Test and Repair and Hierarchical DFX Management of IP in Automotive and AI SoCs

Track: Silicon Test and Analytics

Memory test and repair at 5nm and smaller technologies present new and unique challenges to SoC. With growing process density and complexity, SoC designers need to overcome new memory fault types (specific to each FinFET node) to offer minimal DPPM, while satisfying performance, power and reliability needs specific to new applications like artificial intelligence and automotive. This tutorial will introduce the next generation of TestMAX SMS, Synopsys’ memory test and repair solution including details of the recently announced support for embedded MRAM (eMRAM) technology. The speaker will also discuss the DesignWare SHS, a hierarchical DFX solution for all mixed signal IP, digital logic blocks, and cores on your SoC. The tutorial will cover test, repair, diagnostics as well as in-field self-test capabilities with examples of successful customer case studies.

Presenter(s)
Yervant Zorian

Synopsys

1:25 PM - 1:50 PM

Tower Support for Synopsys' Analog / RF / Photonics Design Flows​

Track: Custom-AMS

This presentation will cover considerations for developing PDKS that deliver maximum productivity to designers of analog, RF and silicon photonics ICs. Tower fully supports the Synopsys Custom Design Platform through a robust set of iPDKs. These include support for advanced productivity features in Custom Compiler, HSPICE models for Synopsys SPICE and FastSPICE simulators, and runsets for IC Validator physical verification and StarRC extraction. We will also provide photonics elements for OptoCompiler for selected process nodes. Plus, the development flow and QA of iPDK, how we enrich it and reference design example for each of the supported process.

Presenter(s)
Ofer Tamir

Managing Director Design Enablement & Support, Tower Semiconductor

7:00 AM - 7:50 AM

GLOBALFOUNDRIES® 22FDX® Digital Automotive Flow Implementing ISO 26262 Functional Safety Mechanisms

Track: Automotive

The presentation introduces GLOBALFOUNDRIES® 22FDX® as the technology and design platform of choice for the next generation of automotive designs. It focuses on how the 22FDX AG1 Automotive digital design platform supports ISO26262 functional safety (FuSa) requirements. Synopsys Design Compiler (DC-NXT) and IC Compiler II toolset based safety-aware digital design flow is described to introduce FuSa features on a safety critical design, implemented with GF 22FDX based Synopsys Automotive Grade 1 (AG-1) 9-track std-cell library. The FuSa features covered are TMR (triple mode redundancy), DMR (double mode redundancy), Fault-tolerant flops, DCLS (dual core lock step) and 100% (or high) RVI (redundant via insertion). Finally, implementation results are summarized, with key focus on the impact assessment of FuSa feature introduction on the PPA results.

Presenter(s)
Nidhish Gaur

GlobalFoundries

8:00 AM - 8:25 AM

*Mitigating Soft Errors Impact on System Reliability

Track: Automotive

Reliability, availability and serviceability is a major concern for cloud applications. Many semiconductor and system companies put emphasis on adding hardware duplication, a costly solution to detect and mitigate failures. A deep analysis of the design can identify the portions of the design that can cause the system to behave unpredictably in the presence of soft errors. Statistical analysis based on probability of error propagation in the design can be performed in large complex systems such as the ones in cloud applications before any testbenches are available. We will present our findings based on the static analysis approach used in TestMAX FuSa to quickly identify the registers most vulnerable to soft errors early in the design development.

Presenter(s)
Ghani Kanawati

Arm

8:25 AM - 8:50 AM

Innovative Design-for-Test (DFT) Methodology for AI & Automotive SoCs

Track: Automotive

In the emerging era of large-scale SoCs comprised of complex IPs, typically designed for AI and automotive applications, it is essential to embrace an innovative approach to overcome numerous DFT challenges. Therefore, a solution must be scalable, robust, and functional safety (FuSa)aware, in addition to meeting the fast time to market aspect. This presentation explains automotive SoC requirements and challenges, as well as an advanced shift-left design-for-test methodology and its criticality. This innovative approach, with the described solution, allows full de-coupling between functional and test design aspects of a safety-critical SoC.

Presenter(s)
Yehonatan Abotbol

Mobileye an Intel Company

9:05 AM - 9:50 AM

Developing Next Generation Automotive Computing Platforms Based on a New Value Chain

Track: KEYNOTE

Future vehicle architectures need to be continuously innovation ready, scalable, a “great” home for software and enable an attractive business case. Building successful scalable architectures for high performance end-2-end use cases requires competences and experiences which are not found in the traditional automotive value chain. The distribution of intelligence within the vehicle and between vehicle and cloud needs to be software driven to enable the desired customer functions, a controllable complexity, new business models and a sustainable as well as affordable life cycle support.

Presenter(s)
Berthold Hellenthal

Head of Computing Platform and Semiconductors, CARIAD, a Volkswagen Group Company

10:00 AM - 10:25 AM

Safe, Secure, Everywhere: ISO 26262 Compliance for Modern Automotive Software

Track: Automotive

Automotive software architectures are changing, and more software than ever is now in scope for functional safety requirements.Organizations who are both new to automotive, or newly in scope for these requirements, sometimes struggle to understand what is needed and formulate an end to end strategy.During this session we discuss how Synopsys has helped leading global automotive suppliers and OEMs achieve ISO 26262 compliance goals with coding standards, fuzz testing, open source management and product cybersecurity strategies and testing.

Presenter(s)
Michael White

Synopsys

10:00 AM - 10:25 AM

STMicroelectronics Memory Verification Flow Optimization Using Synopsys AMS Solutions

Track: Custom-AMS

SPICE verification is required to address today's large memory validation in terms of accuracy, quality of results and acceptable simulation runtime. We will discuss how we have improved our verification flow using Synopsys CustomSim, StarRC and WaveView ADV solutions.

Presenter(s)
Jean-Christophe Lafont

Memory Design Expert, STMicroelectronics

10:00 AM - 10:25 AM

Automating Complex, High-Speed, Interconnect Planning for Next Generation Designs

Track: Digital Design

Typical large-scale ICs contain approximately 30 miles of interconnect. These high-speed "highways" are increasingly becoming the frequency bottleneck in today's most advanced chips. Interconnect design involves numerous steps: planning, pre-convergence, what-if analysis, implementation, etc. Current solutions lack a systematic approach. Instead, they rely on generic desktop tools for design capture and fragmented scripts for design implementation. This ad-hoc approach lacks timing awareness and global optimization. During this session, we will introduce the novel Topology Interconnect Planning (TIP) solution for high-speed-Interconnect design. TIP provides a globally optimized solution that cuts down TAT from days to less than an hour (including timing feedback). It utilizes a unique syntax language that simplifies end-to-end interconnect planning, including repeater and pipeline register locations. TIP significantly improves ease-of-use, and the recipes are re-useable across process nodes and floorplan scaling.

Presenter(s)
Larry Chu

Intel

Presenter(s)
Jose Gomez

Intel

10:00 AM - 10:25 AM

*Instruction Set Verification using Automation and Formal Data Path

Track: Formal Verification

Application Specific Instruction-Set Processors (ASIPs) achieve high performance and flexibility, by using specialized instructions implemented in custom hardware functional units (FUs). Typically, the instruction set is formally represented in a high-level language like C and custom hardware is implemented in RTL. Developing an ASIP’s instruction set involves several optimizations necessary for practical silicon implementation, like resource sharing, pipelining, power, area etc. Verifying functional correctness of the instruction set’s RTL implementation is challenging and time-consuming because of the iterative nature of these optimizations and the very large input space for each instruction. In this presentation, we describe an automated framework which we have developed for constrained-random functional verification and formal techniques used for verification of custom FUs for ASIPs. This framework was used in the verification of 2 ASIPs with very wide (upto 1000s of bits) data paths and was critical in achieving verification closure in significantly shorter time.

Presenter(s)
 Sreenivas Machavaram

Intel

10:00 AM - 10:25 AM

Fusion Based Methodology to Target Peak IR-Drop Reduction Throughout the Implementation Cycle

Track: Low Power Design

We will demonstrate in-design RedHawk Analysis Fusion-based methodology to control IR drop at each step of the implementation cycle. Starting from placement, we perform extensive cell profiling in terms of IR drop along with cell concentration in local pockets, pin density and area hotspot analysis. Leveraging IR drop profiling, we judicially alter cell placement in the hot spots, leading to reduced peak IR drop. At the post-route stage, PG-Augmentation significantly reduces peak IR drop, while being signoff DRC aware. We will discuss the pros and cons of using IR-aware placement as the design in question is a perfect blend of high performance, congestion and power drop. Other analyses such as static IR, dynamic IR (vectored/vectorless), and power EM were also employed. Also, we will discuss how Redhawk Analysis Fusion has helped resolve several data exporting issues, and hence, significantly saved runtime with 100% correlation to standalone RedHawk.

Presenter(s)
Ankit Jain

NXP

10:00 AM - 10:25 AM

Physical Verification Strategies to Scale New-Age Complex Processes and Designs Challenges

Track: Physical Verification

This session presents different strategies and IC Validator features that were employed to debug and resolve design rule violations in a SoC design with multiple Hard-IPs with an overall design size greater than 250 sq-mm. For instance, In-process charging, or Antenna violations need special features to know not only victim gates but also source of aggressor nets involved. Similarly, voltage dependent design rule violations would be easy to debug if one is aware of voltage propagation path or differential voltage that gets considered. The paper also outlines compute resource optimization techniques and throughput improvement that can be achieved for a complex SoC design as above by harnessing multiple features of machine learning and multi-host features supported in IC Validator. The paper even describes correct-by-construction features within ICV that pre-empts design rule violations during placement and routing stages thereby saving multiple cycle times.

Presenter(s)
Mohamed M. Hassaly

Senior Design Automation Engineer, Intel

Presenter(s)
Rajesh Karturi

Intel

10:00 AM - 10:25 AM

*PCIe Gen5 at Speed End-to-End FPGA Prototyping with PHY Daughter Card

Track: Prototyping

Traditionally, it was hard to prototype Intel PCIe controller with Gen3/Gen4/Gen5 end-to-end with actual PCIe devices at speed scenario on FPGA platform. In this presentation, we will propose our whole PCIe Gen5 at speed end-to-end FPGA prototyping solution with PHY daughter card, and the methodology on how to design PASB in order to achieve all the prototyping features we want: all PCIe traffic cycles, speed change, low power features enabled.

Presenter(s)
 Bo Zang

Intel

10:00 AM - 10:25 AM

*Tweak-Your-ECOs "Efficient Way to Generate ECOs"

Track: Signoff I

Current chip design trends indicate exponential growth in instance counts along with usage of newer technology nodes which have stringent/newer physical rules. Another important vector is the development cycle time which is directly linked to time-to-market. In large & high frequency designs, multi-mode, multi-corner timing closure is always a challenge. Accurate physically aware ECO generation is the most important step for quick and predictable design closure. This presentation focuses on how few key features of Tweaker ECO lead to efficient timing convergence of a Multimillion instance design.

Presenter(s)
Sahil Sukheja

Google

10:00 AM - 10:25 AM

*Functional Equivalence Check of Industry’s first eMRAM using Synopsys’ ESP

Track: Signoff II

Magneto-resistive Random Access Memory (MRAM) combines a magnetic device with standard silicon-based microelectronics to obtain the combined attributes of non-volatility, high-speed and unlimited read and write endurance. In this presentation, we would be focusing on how Synopsys’s ESPCV enabled us in the validation of industry’s first eMRAM macro. We will mostly be focusing on the challenges that we faced and how ESPCV helped in overcoming them during the functional validation of eMRAM without impacting our delivery timelines.

Presenter(s)
Jeevan Buddhi

Arm

10:00 AM - 10:25 AM

*Using Functional High-Speed Interfaces for SCAN Test

Track: Silicon Test and Analytics

Increasing gate counts and modern ATPG fault models lead to enormous SCAN data volumes and run times. Conventional parallel scan interfaces cannot transport all this data anymore within a reasonable budget for test time, pins and cost. In addition, some applications like data center servers or self-driving car engines require to run deterministic ATPG patterns in the system regularly, to ensure defect-free operation over the entire lifetime of the device. Here, a standard interface of the device must be used to deliver the test content in-system. This presentation describes a solution to both problems: A scan test controller inside the device drives test data through the scan chains, captures results internally, and communicates with an external host through an available HSIO interface like USB or PCIe. Test data is stored externally and transferred on-demand, allowing for large volumes of scan patterns to be delivered in short time on ATE and in-system.

Presenter
Mike Kozma

Advantest

Presenter
Michael Braun

Advantest

Presenter
Michael Daub

Advantest

10:00 AM - 10:25 AM

What's New in VCS co-simulation with AMS

Track: VCS/Verdi/VIP

Learn more about enhancements in the latest VCS and Verdi releases for real Number Modeling (RNM), Interface Elements(IE) debug and running AMS multi-day simulations.

Presenter(s)
 Vijay Akkaraju

Synopsys

10:25 AM - 10:50 AM

The Future of Automotive Linux: Standardization and Safety

Track: Automotive

For the past decade, Linux in the vehicle has looked much like a traditional embedded system; custom microcontrollers, a one-time software load, and minimal connectivity. Now drivers including ECU consolidation, advanced infotainment and ADAS, 5G connectivity, and customer expectations of continuous functional updates have changed forever the platform requirements for in vehicle compute. A strong ecosystem of standard hardware and software, with extended support and update lifecycles for both security and functionality, is emerging, and functional safety for in-vehicle Linux has also become a rapid requirement. This talk will give an overview of the trajectory of these industry trends.

Presenter(s)
Jered Floyd

RedHat

10:25 AM - 10:50 AM

Performing MOS Reliability Analysis with Variability Using Advanced Monte Carlo Solutions

Track: Custom - AMS

Advancements of technology and scaling down of process increase the impact of process variation on device characteristics and performance. Furthermore, reliability aspects such as hot carrier and bias temperature instability tend to also change the device characteristics over time, thus, combined with process variation they impact circuit robustness. In the presentation, we will show how we are using HSPICE MOSRA modeling capability that allows the accurate prediction of device performance over time.

Presenter(s)
Raed Sabbah

Micron

10:25 AM - 10:50 AM

Getting the Most out of Fusion Compiler with RM 2.0

Track: Digital Design

Fusion Compiler RM 2.0 provides a quick and easy path to deploying best-in-class, R&D recommended technologies and methodologies for your Fusion Compiler design flow. Hit the ground running and stay up to date by using RM2.0. This talk will go through a brief overview of RM 2.0, its optimal configuration, and its intuitive use to get excellent out-of-the-box results. We will additionally share some results on real-world designs. how it’s setup, how to use it to get very good out of the box results, and provide some results on real world designs.

Presenter(s)
Stephen Oetting

Synopsys

10:25 AM - 10:50 AM

Out-of-the-box Performance Impact on Formal Verification Adoption Journey

Track: Formal Verification

Adoption of formal verification includes many steps - education, training, leveraging formal Apps, etc. But conclusive results and fast turnaround is equally important for maximum productivity. Out-of-the-box performance/convergence depends on many core components such as engines, orchestration, regression management, user controls of these components. In this presentation we will discuss how VC Formal has been making use of the latest technologies, such as Machine Learning, to deliver best-in-class out-of-the-box performance.

Presenter(s)
Himanshu Jain

Principal Engineer, Synopsys

Presenter(s)
Ravindra Aneja

Synopsys

10:25 AM - 10:50 AM

Fixing IR Violations Using RedHawk Analysis Fusion with Fusion Compiler

Track: Low Power Design

Ansys RedHawk and RedHawk-SC, the industry standard for sign-off rail analysis are completely integrated within Fusion Compiler to allow users to perform, analyze and fix IR violations. Synopsys Power Integrity flow in Fusion Compiler enables users to analyze and fix dynamic IR violations at various stages of the back-end implementation flow. The following techniques encompassing this flow include: Dynamic power shaping (DPS), IR Driven Placement (IRDP), IR Driven CCD, IR Driven PG Augmentation (PGA). The tutorial will serve as a refresher to the techniques employed in the Synopsys Power Integrity.

Presenter(s)
Krishnaraj Rajan

Synopsys

10:25 AM - 10:50 AM

*Development of Superconductor Advanced Integrated Circuit Design Flow using Synopsys Tools

Track: Physical Verification

HYPRES developed an advanced design flow and design infrastructure for single-flux-quantum (SFQ) superconductor integrated circuits using standard CMOS based EDA tools along with internally developed tools and has been successfully using this flow for the past several years. Using this proven design flow and infrastructure as a knowledge source, we have collaborated with Synopsys to enhance their tools for a full native tool enabled design flow and infrastructure, which represents a significant expansion in design capabilities and capacity for superconducting electronics. This presentation will discuss how we used Synopsys tools for superconductor IC design including spice circuit simulations, plotting waveforms, margins analysis, Monte-Carlo simulations, HDL simulations with timing back-annotation, and IC validation including design rule checker (DRC) and layout-versus-schematic checker (LVS).

Presenter(s)
Jushya Ravi

Hypres

Presenter(s)
Ron Duncan

Synopsys

10:25 AM - 10:50 AM

PCIe Gen5 Validation: The Real World

Track: Prototyping

With few exception any prototype has connectivity to the real world through new protocols. We will show the different options how HAPS prototypes can interface with the real world. Using PCIe Gen5 as an example we will demonstrate why high performance prototypes are critical for system validation.

Presenter(s)
 Rob Parris

Engineering Director, VG group, Synopsys

10:25 AM - 10:50 AM

*Decrypting Paradox of Timing Issues with Tweaker

Track: Signoff I

This presentation details how our flow using tweaker t1 helped us in achieving the signoff quality timing of a design with 30+ million flat instances, hundreds of clocks, drastically squished timeline and huge number of violations at hand at the start of ECO cycle. And when the design became too sensitive to changes, tweaker along with PrimeTime helped in precisely providing feedback for tweaker generated ECOs and accommodating additional ECOs to reduce iteration with PNR.

Presenter(s)
Apoorv Garg

STMicroelectronics

Presenter(s)
RadheShyam Gupta

STMicroelectronics

10:25 AM - 10:50 AM

*A Novel Verification Methodology for Ring Oscillators using ESP

Track: Signoff II

Ring oscillators are very prominently found in modern chip designs as part of the process monitors and sensors used to tune foundry processes and bin manufactured chips. Due to the limitation of formal verification tools, ring oscillator verification has required time consuming SPICE simulations with delay model inaccuracies, extensive measurement parsing, and time-consuming stimulus setup. During this presentation, a novel methodology is proposed using the Synopsys ESP formal equivalence checking tool to verify ring oscillators for, not just basic logic equivalence, but also determine if the implementation consists of the correct number of stages correct cell types, cell sizing, and cell VT as per spec.

Presenter(s)
Shawn Li

Qualcomm

10:25 AM - 10:50 AM

Automated Inking with Silicon Dash in Marvell

Track: Silicon Test and Analytics

Automotive SOCs have strict reliability requirements. One way to guarantee reliability is to isolate potential field failures that pass wafer sort testing and post process them into a failing part to keep them from being built. This re-binning, or inking, is based on statistical analysis. There are many standard algorithms used to accomplish this including DPAT, good die/bad neighborhood, clusters, etc.

In SiliconDash, we show how we can automatically ink parts in an high volume manufacturing environment. We handle the complexity of combining different data sources for single wafer. We apply multiple inking algorithms. Then we automatically send a new build map to assembly.

Presenter(s)
Dexter Rodulfo

Staff Manager Product Engineering, Marvell

10:25 AM - 10:50 AM

*A Framework for Assessing the Vulnerability of ICs Against Fault-Injection Attacks

Track: VCS/Verdi/VIP

Fault-injection attacks have become a major concern for hardware designs, primarily due to their powerful capability in tampering with critical locations in a device to cause violation of its integrity, confidentiality, and availability. Researchers have proposed a number of physical and architectural countermeasures against fault-injection attacks; however, these techniques usually come with large overhead and design efforts making them difficult to use in practice. In addition, the current electronic design automation (EDA) tools are not fully equipped to support vulnerability assessment against fault-injection attacks at the design-time to avoid tedious manual design review. In this paper, we propose an automated framework for fault-injection vulnerability assessment of designs at gate-level using Synopsys Z01X, while considering the design-specific security properties using novel models and metrics. Our experimental results on the security properties of AES, RSA, and SHA implementations show that the security threat from fault-injection attacks can be significantly mitigated by protecting the identified critical locations, which are less than 0.6% of the design.

Presenter(s)
 Huanyu Wang

University of Florida

11:00 AM - 11:50 AM

Replay: GLOBALFOUNDRIES® 22FDX® Digital Automotive Flow Implementing ISO 26262 Functional Safety Mechanisms

Track: Automotive

The presentation introduces GLOBALFOUNDRIES® 22FDX® as the technology and design platform of choice for the next generation of automotive designs. It focuses on how the 22FDX AG1 Automotive digital design platform supports ISO26262 functional safety (FuSa) requirements. Synopsys Design Compiler (DC-NXT) and IC Compiler II toolset based safety-aware digital design flow is described to introduce FuSa features on a safety critical design, implemented with GF 22FDX based Synopsys Automotive Grade 1 (AG-1) 9-track std-cell library. The FuSa features covered are TMR (triple mode redundancy), DMR (double mode redundancy), Fault-tolerant flops, DCLS (dual core lock step) and 100% (or high) RVI (redundant via insertion). Finally, implementation results are summarized, with key focus on the impact assessment of FuSa feature introduction on the PPA results.

Presenter(s)
Nidhish Gaur

GlobalFoundries

11:00 AM - 11:25 AM

*Cosim Using CustomSim and VCS® in FLASH Memory Design

Track: Custom-AMS

Modern FLASH memory design faces many challenges due to increasing complexity and reducing design cycle time. Synopsys Cosim using CustomSim and VCS has provided a good solution. Its user-friendly platform and powerful features makes it a very useful tool in Micron 3D FLAS memory chip design. Not only it offers memory designers another way of simulation, it also demonstrates its flexibility and efficiency in full chip verification, circuit check (cck), EMIR and reliability analysis.

Presenter(s)
David Kao

Micron

Presenter(s)
Raed Sabbah

Micron

11:00 AM - 11:25 AM

*RFSoC Block I/O Optimization

Track: Digital Design

Members of the Xilinx RFSoC implementation team will present on their experiences of delivering highly I/O optimized ~1M instances designs on advanced process nodes. This will include details of the steps required throughout the physical implementation flow to delivery highly optimized I/O designs, including RTL, scan, timing constraint, synthesis, floorplanning, place & route and STA guidelines.

Presenter(s)
Padraig Golden

Senior Physical Design Engineer, Xilinx

Presenter(s)
Paul Ang

Xilinx

Presenter(s)
John McGrath

Xilinx

11:00 AM - 11:25 AM

Unique and Advanced Formal Datapath Validation

Track: Formal Verification

Datapath validation using formal verification is unique in terms of behind the scenes technologies and methodology needed for productive verification. At the same time it has some similarities to traditional formal property checking when it comes to the need for visibility into the complexity of the verification problem and methods and techniques that can be applied for faster performance and better convergence. In this presentation, we will discuss the basics of datapath validation as well as new features making it more convenient for verification/design engineers and formal experts.

Presenter(s)
Neelabja Dutta

Synopsys

11:00 AM - 11:25 AM

Power Integrity and Timing Closure Shift Left with Joint Ansys/Synopsys Customer Solutions

Track: Low Power Design

Power integrity and reliability analyseis are being pulled ever closer to the heart of IC design as silicon processes continue to shrink, design sizes continue to grow, and ultra-low voltage power supplies have eliminated any room for voltage drop or electromigration margins. A major change is that simultaneous switching noise has now come to dominate total IR-drop, which requires expanded activity coverage to catch all possible switching aggressors and avoid frequency loss. Ansys and Synopsys have cooperated to address these issues and developed joint customer solution flows that effectively shift timing closure to the left. We will look at full-flow power integrity with RedHawk-SC and Fusion Compiler from early in-design to incremental IR-drop ECO fixing with Tweaker, and final full- chip signoff. And we will show how the RedHawk-SC integration with PrimeTime automatically detects and fixes IR-drop timing violations to avoid voltage- drop escapes and ensure maximum design performance.

Presenter(s)
Marc Swinnen

Ansys

11:00 AM - 11:25 AM

*Using ICV 3D-IC Verification to Flag Incorrect Die Orientation and Bump Alignment in a Multi-Die Design

Track: Physical Verification

In a 3D multi-die design, it is essential to have the dies placed with correct orientation and bump alignment. A physical verification flow is needed to verify the 3D multi-die design for correctness in the early stage of the design cycle. This presentation discusses how the Synopsys ICC2 tool was used to build a multi-die 3D-IC database and created inputs to run Synopsys ICV 3D-IC verification. We will describe the challenges in building ICC2 3D-IC database with different process nodes. To verify the top and bottom die alignment, the flow created gds and verilog from virtual interface block of the chiplet pairs. We will also discuss how Synopsys ICV 3D-IC verification tool was used to run LVS and DRC on the inputs. Finally, the presentation will discuss the results of the ICV verification runs that provided early design feedback which helped saved weeks of re-work if issues were found during assembly. Future enhancement needed for the virtual block creation for the individual chiplet pairs will also be discussed.

Presenter(s)
Tayib Samu

Graphics Hardware Engineer, Intel

11:00 AM - 11:25 AM

Getting the Most from your Prototyping Farm

Track: Prototyping

Prototyping teams need to deliver maximum usage efficiency to software and system validation teams. We will show how the HAPS Gateway system helps to maximize the value from using HAPS across teams and projects.

Presenter(s)
Jiff Kuo

Sr. Staff Software Engineer, Synopsys

11:00 AM - 11:25 AM

*Bringing Full Chip Leakage Reduction into Reality

Track: Signoff I

Full Chip Leakage reduction on top of Block level power optimization in average contribute additional 10% leakage reduction. The reason is interface, which in average includes 30% of standard cells of a design, leakage reduction which cannot fully utilize at block level. Due to the Full Chip design size, till now signoff based optimization cannot be performed efficiently. The average runtime of a small full chip can reach one week. Presented tool merge modes capability together with divide & concur approach (hierarchical flow) enables runtime reduction to less than a day and 4X reduction in required machine memory with similar QOR and Leakage reduction.

Presenter(s)
Amir Yashfe

Intel

11:00 AM - 11:25 AM

*Formal Verification for Mixed Signal IPs Using ESP: IO Perspective

Track: Signoff II

Our existing methodology of IO verification is cumbersome, and it involves manual testbench creation based on design specifications. Limitation of this flow are high runtime (6hrs for 1 pad) and low vector coverage ( ~40%). With ESPCV, we achieved coverage >90% since tool generates 2n input vectors where n is the number of input pins, and we also saw significant run time reduction of up to 60-70%. In the past, the SoC team has used our models in scenarios which were not explicitly defined in design specification due to complexity involved but supported by design inherently. This led to an inconsistency between Verilog and Spice. We enabled the ESPCV tool successfully for IO designs, which include general purpose, Custom, Dual rail, Single rail etc. We will present the challenges faced and solutions to overcome those, and how the solutions can be extended to other IP Designs.

Presenter(s)
Pulkit Popli

Qualcomm

Presenter(s)
Aditi Satya

Qualcomm

11:00 AM - 11:25 AM

Testbench Debugging Made Easier with Verdi

Track: VCS/Verdi/VIP

With the growing complexity of Testbench, TB debugging has undoubtedly become the most challenging bottleneck in todays’ verification flow. To maximize the efficiency of daily TB debugging process, Verdi automates the instant recall flow for UVM debug. The simulation process and debugging environment at the time when UVM error occurs is kept and recalled automatically, drastically saving debug turnaround time. In addition, Verdi facilitates the dumping and display of class objects and UVM objects. Providing information of dynamic objects and visualization in GUI, taking testbench debug to the next level.

Presenter(s)
Allen Hsieh

Synopsys

11:00 AM - 11:25 AM

Wafer Sort Parameters Post Processing for Assembly Inkless Map Generation

Track: Silicon Test and Analytics

Final test module fails on image sensor related to front-end manufacturing are cost killer and must be understood to quickly recover situation and at least be capable to screen them at wafer sort stage. Some specific optical parameters at final test are not correlated to the one measured at EWS due to test environment constraints. We were capable to build a multivariate linear model on 16 EWS parameters correlating with FT optical fail. Thanks to Silicondash database and scripting capability we have processed EWS wafer database on thousand wafers to generate inking maps for assy plant and save FT cost.

Presenter(s)
Sebastien Desmaison

STMicroelectronics

11:25 AM - 11:50 AM

Improving Productivity and Ease-of-use of COSIM Setup for Analog-centric Users

Track: Custom-AMS

With the growth of circuit complexity, modern SerDes IP designs are set up in COSIM configuration to get the balance of turnaround time and accuracy. The top-level testbench coverage and criteria are usually written by people who have a better knowledge of verification flow and the critical analog blocks are provided by the analog design group. In the presentation, we are going to demonstrate a COSIM setup which is simplified and straightforward for analog centric users. The features offered by VCS and CustomSim COSIM flow allow analog users to add customized settings and stimulus, plus provide an ease-of-debugging solution by enabling merged FSDB feature in Custom WaveView/Verdi.

Presenter(s)
Chuan Lyu

Digital IC Design Engineer, Marvell

11:25 AM - 11:50 AM

*Frequency vs Time Done Right Designing a High-Performance ARM POP IP Solution with Minimal Turn-around Time Using Synopsys Fusion Compiler

Track: Digital Design

As we move towards faster and more powerful devices and ever-smaller technology nodes; we have slowly pushed the number of transistors on a single CPU to soaring levels. This makes the most of the reduction in transistor size and leakage on the latest foundry nodes while pushing the performance of the core to never-seen-before maxima. However, the burgeoning instance count coupled with increasing design and routing complexity exacts a heavy toll on our EDA tools as well as traditional optimization techniques, resulting in extremely large TAT and machine resource usage. In this presentation, we address the solution to this dilemma – the novel CPU POP solution enabled by using Synopsys Fusion Compiler.

Presenter(s)
Viswanath Akash

Arm

11:25 AM - 11:50 AM

Is Formal Signoff a Reality?

Track: Formal Verification

Formal Signoff has had well defined metrics for some time now. These metrics provide a predicable step-by-step path to completeness. These signoff metrics are closely mapped to coverage metrics used in simulation which makes it easier for verification/design engineers. In this presentation, we will review these signoff metrics and share details on how these metrices are setup, calculated and analyzed in a single interactive environment making it intuitive and seamless to signoff on your designs.

Presenter(s)
Sai Karthik Madabhushi

Sr Staff Applications Engineer, Synopsys

11:25 AM - 11:50 AM

*Leakage Recovery Runtime Reduction

Track: Low Power Design

High runtime at subsystem or full-chip flat power recovery is a well-known problem in the VLSI industry. To address this problem, this work sets an aggressive target to complete the power recovery of a subsystem or full-chip flat run within a day after the ECO run is triggered such that a change list will roll into the database on the next day. It is okay to not fix 100% of the design in a single round, and the loop will continue on a daily basis for the next few days. This presentation talks about two native tool features - Machine Learning based power recovery and Split-and-Merge based power recovery to address the high runtime problem. The merits and demerits of both these solutions are discussed and finally we recommend using Split-and-Merge ECO solution specially for the power recovery on the interface paths as this solution can target the interface paths separately.

Presenter(s)
Santanu Kundu

Intel

11:25 AM - 11:50 AM

Design Processing and Verification Using Kubernetes Based Hybrid Cloud Infrastructure

Track: Physical Verification

IBM and Synopsys have been working together to investigate the advantages and trade-offs of migrating high performance EDA applications to the cloud. In this work, we describe the incorporation of synopsys icv validator tools into a digital design flow enabled on a hybrid cloud infrastructure. Large chips require significant compute resource for design and validation of data. Our emphasis in this work is to reduce the process time by running synopsis icv validator applications in kubernetes based containers. Virtual machines are configured with defined cpu and memory requirements. Runtime improvements are realized by taking advantage of icv distributed and multi-threaded capabilities. The advantage of kubernetes is that they can be ported to any cloud environment. We discuss the advantages and disadvantages of running applications using on premis and hybrid cloud models.

Presenter(s)
Clifford Osborn

Senior Engineer, IBM

11:25 AM - 11:50 AM

A Robust Flow for Recreating Obsolete Components using FPGAs

Track: Prototyping

Some custom VLSI technology is approaching 40 years of age. End of life buys and obsolete technology or destroyed mask sets may make buying new parts impossible. Luckily, FPGA technology has become more affordable, faster and large enough to reproduce most VLSI designs or even boards from 20+ years ago. In this presentation, I’ll introduce a flow for re-implementing a legacy design in an FPGA.

Presenter(s)
Frank Bruno

FPGA Engineer, ASIC Solutions

11:25 AM - 11:50 AM

*Timing Convergence with Velocity, Quality and Predictability

Track: Signoff I

It is very challenging to close timing for high frequency designs with clock definition in the order of double digit, gate count greater than 3 million instances and highly congested design. In this presentation, we will discuss targeting to fix hold violations in complex designs, which are highly congested and prone to DRC,PDN,LV, crosstalk and noise. The traditional way is to enable hold corners at the P&R stage, however place & route tools add lots of hold buffers and may complicate the next stages. There is now a new ECO tool for fixing hold violations with velocity and quality. We will share more details of the features and results during this presentation.

Presenter(s)
Arun Jose

Intel

11:25 AM - 11:50 AM

Validating Memory Design Scan Chains from Behavioral to Transistor Level

Track: Signoff II

Silicon wafer test time is a precious and expensive part of delivery of integrated circuits. Scan chains enable fast, high coverage wafer testing. With the increasing complexity of chips at advanced nodes, the importance of incorporating scan chains to test the embedded memories is critical. Full chip scan testing requires high level models of custom design modules. The challenge is proving that these high-level models implement the same scan chain as the custom design. In this session we will discuss ESP, the only solution for validating scan chains from behavioral level models all the way down to transistor level implementations.

Presenter(s)
Rick Eversole

Application Engineer, Synopsys

11:25 AM - 11:50 AM

Demo of SiliconDash: The Next Generation High Volume Semiconductor Big Data Analytics Solution

Track: Silicon Test and Analytics

SiliconDash is the next generation high-volume semiconductor big data analytics solution for fabless companies, IDMs, OSATs and foundries. It provides comprehensive yield management, quality management and throughput management of your IC and MCM (multi-chip module) products throughout the manufacturing and test process. It delivers comprehensive end-to-end real-time intelligence and control of manufacturing and test operations for executives, managers, product engineers, test engineers, quality engineers, sustaining engineers, device engineers, yield engineers and test operators. SiliconDash handles the complex management of test data. It applies analytics algorithms to all your data through its stream compute platform. SiliconDash then turns these analytics into actions through its industry-leading Insights feature.

Presenter(s)
Mark Laird

Applications Engineer, Sr Staff, Synopsys

11:25 AM - 11:50 AM

*Known Issues And Solutions (KIAS): A Way to Capture Solutions of Already Debugged Issues and Present as Information to Users Whenever Error is Logged Again

Track: VCS/Verdi/VIP

KIAS, an acronym for KNOWN ISSUES AND SOLUTIONS, is a way to capture solutions of already debugged issues and present as information to users whenever error is logged again. Two solutions are provided, one using a generic python script that would work for any type of error and is also language independent hence it can be used by software/hardware designers/verification engineers alike and another one using System Verilog UVM.

Presenter(s)
Ronak Dham

Xilinx

Presenter(s)
Sourabh Goyal

Xilinx

12:00 PM - 12:25 PM

Advanced Custom Design & 3DIC Capabilities for Extraction

Track: Custom-AMS

Custom Design market is growing driven by AMS and Co-design opportunities. Couple that with migration to advanced nodes, has brought parasitic extraction to the forefront. There is a constant need to improve capacity, accuracy, productivity & features for PEX tools. In this session you will learn how StarRC is making a strong push in this market with new custom design features, 3DIC support and tight integration with Custom Design Platforms

Presenter(s)
Senthil Annamalai

Synopsys

12:00 PM - 12:25 PM

*Replay: Mitigating Soft Errors Impact on System Reliability

Track: Automotive

Reliability, availability and serviceability is a major concern for cloud applications. Many semiconductor and system companies put emphasis on adding hardware duplication, a costly solution to detect and mitigate failures. A deep analysis of the design can identify the portions of the design that can cause the system to behave unpredictably in the presence of soft errors. Statistical analysis based on probability of error propagation in the design can be performed in large complex systems such as the ones in cloud applications before any testbenches are available. We will present our findings based on the static analysis approach used in TestMAX FuSa to quickly identify the registers most vulnerable to soft errors early in the design development.

Presenter(s)
Ghani Kanawati

Arm

12:00 PM - 12:25 PM

*Convergence Methodology & Optimization Techniques for Complex SoC Channel

Track: Digital Design

With ever-increasing demand for SoC speed, performance, and features, huge and complex SoC design is getting more common. Fully abutted channel-based design is one of the most common methodology for complex SoC floorplanning. Full chip channel will be committed to multiple channel partitions to speed up execution and convergence time. Full chip channel partition could be very challenging in term of integration, route convergence, and timing convergence. A thorough strategic planning and convergence methodology is needed to ensure complex full chip channels can be converged on time without jeopardizing SoC schedule. This presentation will discuss a complete SoC full chip channel convergence methodology and techniques based on the learning from a very huge & complex SoC design (>250mm2) with advance process node.

Presenter(s)
Eng Heng See

Structural Design Engineer, Intel

12:00 PM - 12:25 PM

Chip Level Standard Cell EM Signoff on SoC in PrimePower

Track: Low Power Design

Semiconductor markets such as automotive have high standards for reliability. Cell EM (electro-migration) reliability analysis is used to identify standard cell instance when its output toggle rate exceed the limit established by the foundry. To ensure design reliability, cell EM violations must be found and fixed before final signoff. In this presentation, we will review chip-level EM analysis challenges on multi-million gate SoC design, and PrimePower feature enhancements.

Presenter(s)
Joseph Siu

Qualcomm

12:00 PM - 12:25 PM

Tweaker ECO Technology Innovations for Fastest Path to PPA Closure

Track: Signoff I

Advanced node designs have stringent thresholds of power, performance, area (PPA), which leaves very little tolerance for timing errors and physical layout. In addition, advanced process nodes have much more complicated physical rules to meet, which leads to a higher number of scenarios that need to be simulated to ensure a successful design. To meet aggressive design tapeout schedules, design teams aim to signoff with a much shorter ECO closure cycle time, even as the designs metrics of scenarios and instances are reaching greater than 500 and over two hundred million, respectively. Every ECO change can potentially become a bottleneck and influence the tape out schedule. The ECO solution needs to effectively identify, analyze, fix and recover all of the potential issues in chip performance, power, area and reliability. We will introduce how Synopsys Tweaker ECO Closure Platform can solve these challenges and help you better control their project schedule and achieve the best QoR.

Presenter(s)
Manoj Chacko

Synopsys

12:00 PM - 12:25 PM

*NanoTime Memory for Register File Designs

Track: Signoff II

NanoTime Memory Register File Feature automates the analysis of such Register file designs. This paper explores the setup of NanoTime Memory Register File flow and also discusses the margin checks which are executed automatically. Results of Accuracy correlation between NTM flow and SPICE simulation will also be discussed.

Presenter(s)
Triusa Tan

Broadcom

12:00 PM - 12:25 PM

Implementation and Use of PVT Monitors in Large Die Applications

Track: Silicon Test and Analytics

Large die designs can exhibit many types of variations across the die area. In this presentation we will show the architecture, implementation and use cases for a design that implements more than 100 PVT sensors.

Presenter
Raj Lam

Esperanto

Presenter
Bill Orner

Esperanto

12:00 PM - 12:25 PM

*Fast Coverage Prototyping/Debug Using Waveform Data and Jupyter Notebooks

Track: VCS/Verdi/VIP

In this presentation, we present a faster flow for prototyping and debugging functional coverage, which relies on wave files as a source for coverage data. We will present our work mostly using the SNPS flow that includes Verdi, FSDB and pynpi for accessing FSDB from python. It will present various future-work items needed to streamline the flow and make it easier to setup and productize.

Presenter(s)
Avidan Efody

Intel

12:25 PM - 12:50 PM

Radically Improving Layout Efficiency Through the Use of User Defined Devices (UDD)

Track: Custom-AMS

The use of custom programable cells (PCells) can significantly increase layout efficiency and reuse. This presentation will discuss how the Custom Compiler graphical UDD methodology allows Endura to develop highly reusable programable layout blocks on a variety of technology nodes. These cells ranged from complex routing for power devices as well as reusable analog building blocks. The UDD capability enabled these customisable PCells to be developed at least 2x more efficiently than using traditional approaches and with a degree complexity and sophistication ordinarily beyond the scope of a GUI based tool.

Presenter(s)
Jack Quinn

Endura

12:25 PM - 12:50 PM

Replay: Innovative Design-for-Test (DFT) Methodology for AI & Automotive SoCs

Track: Automotive

In the emerging era of large-scale SoCs comprised of complex IPs, typically designed for AI and automotive applications, it is essential to embrace an innovative approach to overcome numerous DFT challenges. Therefore, a solution must be scalable, robust, and functional safety (FuSa)aware, in addition to meeting the fast time to market aspect. This presentation explains automotive SoC requirements and challenges, as well as an advanced shift-left design-for-test methodology and its criticality. This innovative approach, with the described solution, allows full de-coupling between functional and test design aspects of a safety-critical SoC.

Presenter(s)
Yehonatan Abotbol

Mobileye an Intel Company

12:25 PM - 12:50 PM

*The Next Level of Fusion: Fusion Technology + EMLL + Design Services

Track: Digital Design

Google designs specialized hardware for Machine Learning applications and has traditionally used a model based on Netlist Hand-off to IDMs (Integrated Device Manufacturers). This approach has limited Google’s control over PPA (Performance, Power and Area) of the design. To achieve greater PPA, Google decided to build an in-house Physical Design capability and partnered with Synopsys to do so. This presentation will highlight the many ways in which our multi-faceted partnership with Synopsys helped us push the PPA envelope and set us up for future success.

Presenter(s)
Venkata Rajesh Mekala

Google

Presenter(s)
Hiral Shah

Synopsys

12:25 PM - 12:50 PM

RTL Power Estimation Accuracy - Correlation Study

Track: Low Power Design

One of the biggest problems with RTL power estimation is accuracy comparing against sign-off power. If the estimation is not accurate, designers lose confidence in the tool. There are multiple factors that make power estimation at the RTL level challenging. Clock tree modeling is not accurate at the RTL level because CTS is only done during implementation. Clock tree power contributes up to 30% of the overall power for some workloads. Estimation without timing and physical awareness also causes power miscorrelation. Finally using different synthesis engines between RTL power estimation and implementation also contributes to miscorrelation. Addressing these issues requires a RTL power estimation solution that is timing and physical aware and models clock tree topologies as actual implementation. This presentation covers the extensive correlation study conducted on multiple Intel projects using this type of solution..

Presenter(s)
Wayne H. Szeto

Senior Component Engineer, Intel

12:25 PM - 12:50 PM

NanoTime Signal Integrity for Advanced Process Nodes

Track: Signoff II

Signal integrity (SI) has been a major concern in custom design and signoff for a few years. NanoTime has been continuously upgrading its feature set to accurately account for SI effects. In the noise domain, effects such as driver weakening and load-induced noise became more prevalent. Given that stages are affected by noise waveforms coming from both drivers and fanouts, advanced reporting capabilities are required to guide designers into which stages should be investigated first. In this tutorial, we review basic SI concepts for timing and noise, and we focus on recently added SI features that target advanced process nodes. The presentation should enable NanoTime users to extract the most value out of their SI results.

Presenter(s)
David Wu

Synopsys

12:25 PM - 12:50 PM

Introduction to Embedded In-Chip Sensing & PVT Monitoring

Track: Silicon Test and Analytics

In-chip sensors and PVT monitors are semiconductor IP circuits that are typically embedded inside of system-on-chip (SoC) designs. Sensing the dynamic operating environment of the SoC (i.e., the voltage and temperature) as well as the static condition (i.e., process) provides a method to optimize the SoCs performance based on the local conditions the chip is experiencing. These monitors and sensors represent embedded analog IP blocks that are typically integrated into SoCs with the goal of sensing the process variability and operating environment of the chip. These devices exploit the fact that certain measurable characteristics of a semiconductor device change depending on levels of activity and provide a level of visibility into SoC operation that is simply unavailable any other way. The technology is also used as the device is deployed in the field to measure and optimize performance.

Presenter(s)
Richard McPartland

Synopsys

12:25 PM - 12:50 PM

Beyond RAL - Improved Solutions for Advanced Registers Structures

Track: VCS/Verdi/VIP

The UVM Register Abstraction Layer (RAL) is used for modeling registers and memories of the DUT. However, there are cases where one needs to implement some non-trivial features over the RAL class. This presentation will discuss a few of these cases related to Indirect Access Registers, Multilingual Adapter, Multiple Masters.

Presenter(s)
Elihai Maicas

Nvidia

Presenter(s)
Matt Orsini

Nvidia

Presenter(s)
Matt Trostel

Nvidia

1:00 PM - 1:25 PM

*Migrating to Fusion Compiler™ from Design Compiler, Design-for-Test & IC Compiler II Has Never Been so Easy!

Track: Digital Design

A presentation about the benefits of using Fusion Compiler over the traditional Synopsys tools like Design Compiler Design for TestFT, IC Compiler II. Advantages like shorter run-times, better performance, easy DFT integration, higher utilization, reduction in total area, and more will be given as examples. Besides the advantages of using one platform that combines and contains all the toolsets, what makes it more productive to the end-user is the inner integration level between those individual tools when they are grouped under FC. Also, how in Microsoft the switch to Fusion Compiler, under a very demanding and stressful timeline was gone smoothly while meeting the due date even before expectations. Emphasizing that following the reference manual and using the automatic conversion scripts short the ramp-up time compared to a full end to end flow bring up from scratch.

Presenter(s)
Aviad Ben-Haim

Microsoft

1:00 PM - 1:25 PM

RTL Power Exploration with PrimePower RTL

Track: Low Power Design

Low power, energy efficient SoC design requires accurate analysis to identify power problems early, during the RTL stage. PrimePower RTL is a fast, physically-and-timing-aware power estimation solution that enables designers to analyze, explore, and optimize their RTL with confidence, improving power and shortening the design cycle. This tutorial highlights key PrimePower technologies enabling RTL power exploration. An example design illustrates the flow showing how to quickly identify power problems, use RTL power metrics and cross-probing to understand root causes, explore solutions using what-if analysis, and reduce RTL power by improving clock-gating efficiency, register gating, glitch power, and more.

Presenter(s)
Jon Worthington

Synopsys

1:00 PM - 1:25 PM

The Lastest Technoloy Updates for Failure Analysis Solution of Samsung Foundry Silicon

Track: Silicon Test and Analytics

Improving silicon yield requires an intensive understanding of silicon failures. For this understanding, failure analysis technologies and methodologies are mandatory to ensure cost-effective product manufacturing. Working with Synopsys, Samsung Foundry has collaborated on future-oriented failure analysis methodology. In this presentation, you will hear about the latest technology updates for failure analysis solution of Samsung Foundry silicon and see examples of its application. Techniques and schemes, such as transistor-level, defect trend, and volume diagnostics using Yield Explorer will be covered.

Presenter(s)
Jaeseok Park

Samsung Electronics

1:25 PM - 1:50 PM

Demo of Yield Explorer: Standard Volume Diagnostic Analysis Flow of Both Logic & Memory

Track: Silicon Test and Analytics

Nanometer node yield issues are dominated by design-process-test interactions, mandating cross-domain analyses to mitigate these issues rapidly. Yield Explorer brings yield relevant data from diverse sources such as the physical design flow, wafer manufacturing, and wafer and chip level testing into a single data bank. With the widest possible range of data at their disposal, users achieve unsurpassed clarity in root cause analysis when faced with systematic yield limiters. Yield Explorer achieves this with an order of magnitude advantage in analysis speed in the most complex of use casesfor example, 10X faster volume diagnostics analysis of ATPG output. This significant analysis capability and speed advantage sets Yield Explorer in a class apart from previous yield management systems and enables, for the first time, true connectivity to EDA tools.

Presenter(s)
Michael Hall

Applications Engineer, Sr Staff, Synopsys